PF38F2030W0YTQ2 Micron Technology Inc, PF38F2030W0YTQ2 Datasheet - Page 15

• Manufacturer Part Number: PF38F2030W0YTQ2
• Manufacturer: Micron Technology Inc

Specifications of PF38F2030W0YTQ2

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

128-Mbit W18 Family with Synchronous PSRAM
Table 4:
November 2007
Order Number: 311760-10
R-OE#
F-RST#
WAIT
F-WE#
R-WE#
F-WP#
P-CRE
P-MODE#
P[2:1]-
CS#
S-CS1#
S-CS2
R-UB#
R-LB#
Power Signals
F-VPP
F[2:1]-
VCC
Symbol
Output
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Signal Descriptions (Sheet 2 of 3)
RAM OUTPUT ENABLE: PSRAM- and SRAM-specific signal; low-true input.
When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE#
disables the output drivers of the selected memory die and places the output drivers in High-Z if
present. Otherwise it is an RFU.
FLASH RESET: Flash-specific signal; low-true input.
When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables
normal operation.
WAIT: Flash- and Synchronous PSRAM-specific signal; configurable true-level output.
When asserted, WAIT indicates invalid output data. When deasserted, WAIT indicates valid output
data.
FLASH WRITE ENABLE: Flash-specific signal; low-true input.
When low, F-WE# enables Write operations for the enabled flash die. Address and data are latched
on the rising edge of F-WE#.
RAM WRITE ENABLE: PSRAM- and SRAM-specific signal; low-true input.
When low, R-WE# enables Write operations for the selected memory die. Data is latched on the
rising edge of R-WE# if present. Otherwise it is an RFU.
FLASH WRITE PROTECT: Flash-specific signals; low-true inputs.
When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the Lock-
Down function, enabling locked-down blocks to be unlocked with the Unlock command.
PSRAM CONTROL REGISTER ENABLE: Synchronous PSRAM-specific signal; high-true input.
When high, P-CRE enables access to the PSRAM Refresh Control Register (P-RCR) or Bus Control
Register (P-BCR). When low, P-CRE enables normal Read or Write operations if present. Otherwise
it is an RFU.
PSRAM MODE#: Asynchronous only PSRAM-specific signal; low-true input.
When low, P-MODE# enables access to the PSRAM configuration register, and to enter or exit Low-
Power mode. When high, P-MODE# enables normal Read or Write operations if present. Otherwise
it is an RFU.
PSRAM CHIP SELECT: PSRAM-specific signal; low-true input.
When low, P-CS# selects the associated PSRAM memory die. When high, P-CS# deselects the
associated PSRAM die. PSRAM die power is reduced to standby levels, and its data and WAIT
outputs are placed in a High-Z state.
SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input.
When both S-CS1# and S-CS2 are asserted, the SRAM die is selected. When either S-CS1# or
S-CS2 is deasserted, the SRAM die is deselected.
RAM UPPER/LOWER BYTE ENABLES: PSRAM- and SRAM-specific signals; low-true inputs.
When low, R-UB# enables DQ[15:8] and R-LB# enables DQ[7:0] during PSRAM or SRAM Read and
Write cycles. When high, R-UB# masks DQ[15:8] and R-LB# masks DQ[7:0] if present. Otherwise
it is an RFU.
FLASH PROGRAM/ERASE VOLTAGE: Flash specific.
F-VPP supplies program or erase power to the flash die.
FLASH CORE POWER SUPPLY: Flash specific.
• WAIT is driven whenever the flash or the synchronous PSRAM is selected and its output enable
• WAIT is High-Z whenever flash or the synchronous PSRAM is deselected, or its output enable
• Flash and PSRAM must configure the WAIT RCR bit to be the same true-level state.
• P1-CS# is dedicated to PSRAM die #1 if present. Otherwise it is an RFU.
• P2-CS# is dedicated to PSRAM die #2 if present. Otherwise it is an RFU.
• S-CS1# and S-CS2 are dedicated to SRAM if present. Otherwise it is an RFU.
• F[2:1]-VCC supplies the core power to the flash dies.
• F2-VCC is recommended to be tied to F1-VCC, else it is an RFU.
is low.
is high.
Signal Descriptions
Datasheet
Note
3
3
2
2
3
3
3
s
15