AM41DL6408G85I Spansion Inc., AM41DL6408G85I Datasheet - Page 59

• Manufacturer Part Number: AM41DL6408G85I
• Manufacturer: Spansion Inc.

Specifications of AM41DL6408G85I

• Lead Free Status / RoHS Status: Supplier Unconfirmed

AC CHARACTERISTICS
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
2. t
3. t
4. t
5. A write occurs during the overlap (t
58
when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation.
A write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
CE1#s
CE2s
Address
UB#s, LB#s
WE#
Data In
Data Out
Figure 32. SRAM Write Cycle—UB#s and LB#s Control
WP
) of low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low
High-Z
(See Note 4)
t
P R E L I M I N A R Y
AS
Am41DL6408G
(See Note 2)
WR
t
CW
t
t
AW
WC
applied in case a write ends as CE1#s or WE# going high.
(See Note 5)
t
t
CW
(See Note 2)
BW
t
WP
t
DW
Data Valid
WP
t
WR
t
is measured from the beginning of write
DH
(See Note 3)
High-Z
August 19, 2002