AM41DL6408G85I Spansion Inc., AM41DL6408G85I Datasheet
AM41DL6408G85I
Specifications of AM41DL6408G85I
Related parts for AM41DL6408G85I
AM41DL6408G85I Summary of contents
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Am41DL6408G Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, ...
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PRELIMINARY Am41DL6408G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 64 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit ( 8-Bit/512 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS ...
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GENERAL DESCRIPTION Am29DL640G Features The Am29DL640G megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . ...
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SRAM Write Cycle .................................................................. 56 Figure 30. SRAM Write Cycle—WE# Control ................................. 56 Figure 31. SRAM Write Cycle—CE1#s Control .............................. 57 Figure 32. SRAM Write Cycle—UB#s and LB#s Control................ 58 Flash Erase And Programming Performance . . . 59 Latchup ...
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PRODUCT SELECTOR GUIDE Part Number Speed Standard Voltage Range: Options V = 2.7–3 Max Access Time (ns) CE#f Access (ns) OE# Access (ns) MCP BLOCK DIAGRAM A21 to A0 A21 to A0 A–1 WP#/ACC RESET# CE#f CIOf A0 ...
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FLASH MEMORY BLOCK DIAGRAM Mux A21–A0 RY/BY# A21–A0 STATE RESET# CONTROL WE# & CE# COMMAND REGISTER BYTE# WP#/ACC DQ15–DQ0 A21–A0 Mux OE# BYTE# Bank ...
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CONNECTION DIAGRAM LB UB A18 A17 DQ1 ...
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PIN DESCRIPTION A18– Address Inputs (Common) A21–A19, A Address Inputs (Flash Highest Order Address Pin (SRAM) Byte mode DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) ...
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... SRAM DEVICE DENSITY Mbits Order Number Am41DL6408G70I Am41DL6408G85I Am41DL6408G71I needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-3 lists the device bus operations, the inputs and control levels they require, and the result- ing output ...
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Table 1. Device Bus Operations—Flash Word Mode, CIOf = V Operation CE#f CE1#s CE2s OE# WE# (Notes Read from Flash Write to Flash Standby 0 Output Disable ...
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Table 2. Device Bus Operations—Flash Word Mode, CIOf = V Operation CE#f CE1#s CE2s OE# WE# SA (Notes Read from Flash Write to Flash ...
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Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V Operation CE#f CE1#s CE2s OE# WE# SA (Notes Read from Flash Write to Flash ...
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Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V Operation CE#f CE1#s CE2s OE# WE# (Notes Read from Flash Write to Flash Standby ...
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The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this ...
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If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed the table represents the standby current spec- CC3 ification. Automatic Sleep Mode The automatic sleep mode minimizes ...
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Table 5. Am29DL640G Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA23 0010000xxx SA24 0010001xxx SA25 0010010xxx SA26 0010011xxx SA27 0010100xxx SA28 0010101xxx SA29 0010110xxx SA30 0010111xxx SA31 0011000xxx SA32 0011001xxx SA33 0011010xxx SA34 0011011xxx SA35 0011000xxx SA36 0011101xxx SA37 ...
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Table 5. Am29DL640G Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA71 1000000xxx SA72 1000001xxx SA73 1000010xxx SA74 1000011xxx SA75 1000100xxx SA76 1000101xxx SA77 1000110xxx SA78 1000111xxx SA79 1001000xxx SA80 1001001xxx SA81 1001010xxx SA82 1001011xxx SA83 1001100xxx SA84 1001101xxx SA85 ...
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Table 5. Am29DL640G Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA119 1110000xxx SA120 1110001xxx SA121 1110010xxx SA122 1110011xxx SA123 1110100xxx SA124 1110101xxx SA125 1110110xxx SA126 1110111xxx SA127 1111000xxx SA128 1111001xxx SA129 1111010xxx Bank 4 SA130 1111011xxx SA131 1111100xxx SA132 ...
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Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see ...
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The alternate method intended only for programming equipment requires V on address pin A9 and OE#. ID This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. The device is shipped with all sectors unprotected. ...
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START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a ...
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The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until V is greater than V CC system must provide the proper signals to the ...
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Addresses Addresses (Word Mode) (Byte Mode) 1Bh 36h 1Ch 38h 1Dh 3Ah 1Eh 3Ch 1Fh 3Eh 20h 40h 21h 42h 22h 44h 23h 46h 24h 48h 25h 4Ah 26h 4Ch Addresses Addresses (Word Mode) (Byte Mode) 27h 4Eh 28h 50h ...
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Table 13. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah 94h 4Bh 96h 4Ch 98h 4Dh 9Ah ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 14 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper ...
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The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 14 shows the address and data requirements for ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 14 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase ...
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DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for infor- mation on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- ...
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Table 14. Am29DL640G Command Definitions Command Sequence (Note 1) Addr Read (Note Reset (Note 7) 1 XXX Word 555 Manufacturer ID 4 Byte AAA Word 555 Device ID (Note 9) 6 Byte AAA Word 555 SecSi Sector ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 15 and the following subsections describe the function of these bits. DQ7 and DQ6 each ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . – +125 C Ambient Temperature with Power Applied . . . . . . . . ...
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DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I RESET# Input Load Current LIT I Output Leakage Current LO I ACC Input Leakage Current LIA Flash V Active Read Current CC1 (Notes ...
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Notes: 1. The I current listed is typically less than 2 mA/MHz, with OE Maximum I specifications are tested with active while Embedded Erase or Embedded Program is in progress ...
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DC CHARACTERISTICS SRAM DC AND OPERATING CHARACTERISTICS Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current LO I Operating Power Supply Current Average Operating Current CC1 I s Average Operating Current CC2 V ...
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DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6 Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 12. Input Waveforms ...
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AC CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 13. Timing Diagram for Alternating Between SRAM to Flash August 19, 2002 ...
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AC CHARACTERISTICS Flash Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
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AC CHARACTERISTICS Word/Byte Configuration (CIOf) Parameter JEDEC Std Description t t CE#f to CIOf Switching Low or High ELFL/ ELFH t CIOf Switching Low to Output HIGH Z FLQZ t CIOf Switching High to Output Active FHQV CE#f OE# CIOf ...
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AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t t ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f t GHWL OE# WE Data RY/BY VCS Notes program address program data Illustration shows ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f t GHWL OE WE Data 55h RY/BY# t VCS Notes: 1. SADD = sector address (for Sector Erase), ...
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AC CHARACTERISTICS t WC Addresses Valid CE#f OE WE# t WPH Valid Data In WE# Controlled Write Cycle Figure 21. Back-to-back Read/Write Cycle Timings t RC Addresses VA t ACC t CE ...
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AC CHARACTERISTICS Addresses CE#f t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read ...
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AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary Sector t RSP Unprotect RESET# Hold ...
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AC CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE#f WE# OE# * For sector protect For sector unprotect, A6 ...
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AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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AC CHARACTERISTICS SRAM Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time Chip Enable to Output CO1 CO2 t Output Enable Access Time OE t LB#s, UB#s to Access Time BA ...
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AC CHARACTERISTICS Address CE#1s CE2s OE# Data Out High-Z Notes CIOs is low, ignore UB#s/LB#s timing and t are defined as the time at which the outputs achieve the open circuit ...
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AC CHARACTERISTICS SRAM Write Cycle Parameter Description Symbol t Write Cycle Time WC t Chip Enable to End of Write Cw t Address Setup Time AS t Address Valid to End of Write AW t UB#s, LB#s to End of ...
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AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing measured from CE1#s going low to the end of write ...
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AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. UB#s and LB#s controlled, CIOs must be high measured from CE1#s going low to the end of write measured ...
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FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Byte Mode Chip Program Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the ...
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SRAM DATA RETENTION Parameter Parameter Description Symbol V V for Data Retention Data Retention Current DR t Data Retention Set-Up Time SDR t Recovery Time RDR Notes: 1. CE1#s V – 0.2 V, CE2s V – 0.2 ...
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PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm August 19, 2002 Am41DL6408G 61 ...
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REVISION SUMMARY Revision A (October 24, 2001) Initial release. Revision A+1 (November 26, 2001) Global The abbreviation for Sector Address has been changed from SA to SADD. Connection Diagrams Changed ball E4 to “Shared” coloring. Tables 1–4, Device Bus Operations ...