AM41DL6408G85I Spansion Inc., AM41DL6408G85I Datasheet - Page 4

• Manufacturer Part Number: AM41DL6408G85I
• Manufacturer: Spansion Inc.

Specifications of AM41DL6408G85I

• Lead Free Status / RoHS Status: Supplier Unconfirmed

TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
flash memory Block Diagram . . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Common Flash Memory Interface (CFI) . . . . . . . 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
August 19, 2002
Special Handling Instructions for FBGA Package .................... 7
Word/Byte Configuration ........................................................ 13
Requirements for Reading Array Data ................................... 13
Writing Commands/Command Sequences ............................ 14
Simultaneous Read/Write Operations with Zero Latency ....... 14
Standby Mode ........................................................................ 14
Automatic Sleep Mode ........................................................... 15
RESET#: Hardware Reset Pin ............................................... 15
Output Disable Mode .............................................................. 15
Sector/Sector Block Protection and Unprotection .................. 19
Write Protect (WP#) ................................................................ 20
Temporary Sector Unprotect .................................................. 20
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 22
Hardware Data Protection ...................................................... 22
Reading Array Data ................................................................ 26
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ..
26
Byte/Word Program Command Sequence ............................. 27
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
SRAM Word Mode, CIOs = V
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
SRAM Byte Mode, CIOs = V
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SRAM Word Mode, CIOs = V
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
Byte Mode, CIOs = V
Accelerated Program Operation .......................................... 14
Autoselect Functions ........................................................... 14
Table 5. Am29DL640G Sector Architecture ....................................15
Table 6. Bank Address ....................................................................18
Table 7. SecSi Sector Addresses ...............................................18
Table 8. Am29DL640G Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................19
Table 9. WP#/ACC Modes ..............................................................20
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21
Low V
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ...................................................................... 23
Power-Up Write Inhibit ......................................................... 23
Table 10. CFI Query Identification String ........................................ 23
System Interface String................................................................... 24
Table 12. Device Geometry Definition ............................................ 24
Table 13. Primary Vendor-Specific Extended Query ...................... 25
Unlock Bypass Command Sequence .................................. 27
CC
Write Inhibit ........................................................... 22
SS
..................................................................13
SS
CC
CC
..................................................... 10
......................................................11
.....................................................12
P R E L I M I N A R Y
IL
; SRAM
SS
IH
IH
Am41DL6408G
;
;
;
Write Operation Status . . . . . . . . . . . . . . . . . . . . 31
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
SRAM DC and Operating Characteristics . . . . . 38
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ........................... 29
DQ7: Data# Polling ................................................................. 31
RY/BY#: Ready/Busy# ............................................................ 32
DQ6: Toggle Bit I .................................................................... 32
DQ2: Toggle Bit II ................................................................... 33
Reading Toggle Bits DQ6/DQ2 ............................................... 33
DQ5: Exceeded Timing Limits ................................................ 33
DQ3: Sector Erase Timer ....................................................... 33
CMOS Compatible .................................................................. 36
SRAM CE#s Timing ................................................................ 41
Flash Read-Only Operations ................................................. 42
Hardware Reset (RESET#) .................................................... 43
Word/Byte Configuration (CIOf) .............................................. 44
Erase and Program Operations .............................................. 45
Temporary Sector Unprotect .................................................. 50
Alternate CE#f Controlled Erase and Program Operations .... 52
SRAM Read Cycle .................................................................. 54
Figure 3. Program Operation ......................................................... 28
Figure 4. Erase Operation.............................................................. 29
Table 14. Am29DL640G Command Definitions .............................. 30
Figure 5. Data# Polling Algorithm .................................................. 31
Figure 6. Toggle Bit Algorithm........................................................ 32
Table 15. Write Operation Status ................................................... 34
Figure 7. Maximum Negative Overshoot Waveform ...................... 35
Figure 8. Maximum Positive Overshoot Waveform........................ 35
Figure 9. I
Automatic Sleep Currents) ............................................................. 39
Figure 10. Typical I
Figure 11. Test Setup.................................................................... 40
Figure 12. Input Waveforms and Measurement Levels ................. 40
Figure 13. Timing Diagram for Alternating Between SRAM to Flash ..
41
Figure 14. Read Operation Timings ............................................... 42
Figure 15. Reset Timings............................................................... 43
Figure 16. CIOf Timings for Read Operations................................ 44
Figure 17. CIOf Timings for Write Operations................................ 44
Figure 18. Program Operation Timings.......................................... 46
Figure 19. Accelerated Program Timing Diagram.......................... 46
Figure 20. Chip/Sector Erase Operation Timings .......................... 47
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 48
Figure 22. Data# Polling Timings (During Embedded Algorithms). 48
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 49
Figure 24. DQ2 vs. DQ6................................................................. 49
Figure 25. Temporary Sector Unprotect Timing Diagram .............. 50
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 51
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 53
Figure 28. SRAM Read Cycle—Address Controlled...................... 54
Figure 29. SRAM Read Cycle ........................................................ 55
CC1
Current vs. Time (Showing Active and
CC1
vs. Frequency ............................................ 39
3