AD9852ASQ Analog Devices Inc, AD9852ASQ Datasheet - Page 26

• Manufacturer Part Number: AD9852ASQ
• Manufacturer: Analog Devices Inc

Specifications of AD9852ASQ

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AD9852
The 32-bit automatic I/O update counter can be used to
construct complex chirp or ramped FSK sequences. Because
this internal counter is synchronized with the AD9852 system
clock, it allows precisely timed program changes to be invoked.
Therefore, the user is only required to reprogram the desired
registers before the automatic I/O update clock is generated.
In chirp mode, the destination frequency is not directly speci-
fied. If the user fails to control the chirp, the DDS naturally
confines itself to the frequency range between dc and Nyquist.
Unless terminated by the user, the chirp continues until power
is removed.
When the chirp destination frequency is reached, there are
several possible outcomes:
1.
2.
3.
4.
Stop at the destination frequency using the HOLD pin, or
by loading all 0s into the delta frequency word registers of
the frequency accumulator (ACC1).
Use the HOLD pin function to stop the chirp, and then ramp
down the output amplitude using the digital multiplier stages
and the shaped-keying pin, Pin 30, or via program register
control (Address 21 hex to Address 24 hex).
Abruptly terminate the transmission with Bit CLR ACC2.
Continue chirp by reversing the direction and returning to
the previous, or another, destination frequency in a linear
or user-directed manner. If this involves going down in
frequency, a negative 48-bit delta frequency word (the
MSB is set to 1) must be loaded into Register 10 hex to
RAMP RATE
I/O UD CLK
MODE
HOLD
DFW
FREQUENCY
TW1
000 (DEFAULT)
F1
0
0
Figure 44. Illustration of HOLD Function
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DELTA FREQUENCY WORD
011 (CHIRP)
RAMP RATE
5.
BPSK (MODE 100)
Binary, biphase, or bipolar phase shift keying is a means to
rapidly select between two preprogrammed, 14-bit output phase
offsets. The logic state of BPSK, Pin 29, controls the selection of
Phase Adjust Register 1 or Phase Adjust Register 2. When low,
BPSK selects Phase Adjust Register 1; when high, it selects
Phase Adjust Register 2. Figure 45 illustrates phase changes
made to four cycles of an output carrier.
Basic BPSK Programming Steps
1.
2.
3.
4.
If higher order PSK modulation is desired, the user can select
single-tone mode and program Phase Adjust Register 1 using
the serial or high speed parallel programming bus.
F1
Register 15 hex. Any decreasing frequency step of the delta
frequency word requires the MSB to be set to logic high.
Continue chirp by immediately returning to the beginning
frequency (F1) in a sawtooth fashion, and repeat the
previous chirp process. This is where the CLR ACC1
control bit is used. An automatic repeating chirp can be set
up using the 32-bit update clock to issue the CLR ACC1
command at precise time intervals. Adjusting the timing
intervals or changing the delta frequency word changes the
chirp range. It is incumbent upon the user to balance the
chirp duration and frequency resolution to achieve the
proper frequency range.
Program a carrier frequency into Frequency Tuning Word 1.
Program appropriate 14-bit phase words into Phase Adjust
Register 1 and Phase Adjust Register 2.
Attach the BPSK data source to Pin 29.
Activate the I/O update clock when ready.