AD9852ASQ Analog Devices Inc, AD9852ASQ Datasheet - Page 19

no-image

AD9852ASQ

Manufacturer Part Number
AD9852ASQ
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9852ASQ

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9852ASQ
Manufacturer:
AD
Quantity:
5 510
Part Number:
AD9852ASQ
Manufacturer:
ADI
Quantity:
258
Part Number:
AD9852ASQZ
Manufacturer:
ADI
Quantity:
2
Part Number:
AD9852ASQZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
MODES OF OPERATION
There are five programmable modes of operation of the AD9852.
Selecting a mode requires that three bits in the control register
(Parallel Address 1F hex) be programmed as shown in Table 5.
Table 5. Mode Selection Table
Mode 2
0
0
0
0
1
In each mode, engaging certain functions may not be
permitted.
Table 6 shows a listing of some important functions and their
availability for each mode.
SINGLE-TONE (MODE 000)
When MASTER RESET is asserted, single-tone mode becomes
the default. The user may also access this mode by programming
it into the control register. The phase accumulator, responsible
for generating an output frequency, is presented with a 48-bit
value from the Frequency Tuning Word 1 registers with default
values of 0. Default values from the remaining applicable registers
further define the single-tone output signal qualities.
The default values after a MASTER RESET configures the
device with an output signal of 0 Hz and 0 phase. Upon power-
up and reset, the output from both DACs is a dc value equal to
the midscale output current. This is the default mode amplitude
setting of 0. Refer to the REFCLK Multiplier section for further
explanation of the output amplitude control. It is necessary to
program all or some of the 28 program registers to produce a
user-defined output signal.
Mode 1
0
0
1
1
0
MASTER RESET
I/O UD CLK
Mode 0
0
1
0
1
0
MODE
FREQUENCY
TW1
000 (DEFAULT)
F1
0
0
Result
Single-tone
FSK
Ramped FSK
Chirp
BPSK
Figure 32. Default State to User-Defined Output Transition
Rev. D | Page 19 of 52
000 (SINGLE TONE)
Figure 32 graphically shows the transition from the default
condition (0 Hz) to a user-defined output frequency (F1).
As with all Analog Devices DDSs, the value of the frequency
tuning word is determined using the following equation:
where:
N is the phase accumulator resolution (48 bits in this instance).
Desired Output Frequency is expressed in hertz.
FTW (frequency tuning word) is a decimal number.
Once a decimal number has been calculated, it must be rounded
to an integer and then converted to binary format—a series of
48 binary-weighted 1s and 0s. The fundamental sine wave DAC
output frequency range is from dc to one-half SYSCLK.
Changes in frequency are phase-continuous, thus the first
sampled phase value of the new frequency is referenced in time
from the last sampled phase value of the previous frequency.
The 14-bit phase register adjusts the cosine DAC’s output phase.
The single-tone mode allows the user to control the following
signal qualities:
Furthermore, all of these qualities can be changed or modulated
via the 8-bit parallel programming port at a 100 MHz parallel-
byte rate, or at a 10 MHz serial rate. Incorporating this attribute
permits FM, AM, PM, FSK, PSK, and ASK operation in the
single-tone mode.
o
o
o
F1
FTW = (Desired Output Frequency × 2
Output frequency to 48-bit accuracy
Output amplitude to 12-bit accuracy
Output phase to 14-bit accuracy
Fixed, user-defined amplitude control
Variable, programmable amplitude control
Automatic, programmable, single-pin-controlled,
shaped on/off keying
N
)/SYSCLK
AD9852

Related parts for AD9852ASQ