ADRF6510ACPZ-WP Analog Devices Inc, ADRF6510ACPZ-WP Datasheet - Page 21

• Manufacturer Part Number: ADRF6510ACPZ-WP
• Manufacturer: Analog Devices Inc

Specifications of ADRF6510ACPZ-WP

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Supplier Unconfirmed

EXAMPLE BASEBAND INTERFACE
The noise spectral density of the ADRF6510 outside the filter
bandwidth is limited by the fixed VGA output noise. It may be
necessary to use an external, fixed-frequency, passive filter prior
to an analog-to-digital conversion to prevent noise aliasing from
degrading the signal-to-noise ratio. As shown in Figure 46 and
Figure 47, the noise density at higher frequencies tends to be flat,
and any higher IF noise aliasing into the Nyquist zone has minimal
effects. Using the AD9639, a 12-bit ADC with a 210 MSPS sam-
pling rate, the effects of an antialiasing filter present between the
ADRF6510 and the ADC showed a minimal 1.5 dB improvement.
When designing an antialiasing filter, it is necessary to consider
the overall source and load impedance presented by the
ADRF6510 and the ADC input to design the filter network. The
differential baseband output impedance of the ADRF6510 is
20 Ω and is designed to drive a high impedance ADC input. It
may be desirable to terminate the ADC input to a lower
impedance by using a terminating resistor, such as 500 Ω. The
terminating resistor helps to better define the input impedance
at the ADC input at the cost of a slightly reduced gain.
The order and type of filter network depend on the desired high
frequency rejection required, the pass-band ripple, and the
group delay. Filter design tables provide outlines for various
filter types and orders, illustrating the normalized inductor and
capacitor values for a 1 Hz cutoff frequency and 1 Ω load. After
scaling the normalized prototype element values by the actual
desired cutoff frequency and load impedance, the series
reactance elements are halved to realize the final balanced filter
network component values.
V
POS
0.1µF
0.1µF
V
POS
100pF
100pF
120nH
1000pF
1
2
3
4
5
6
RFC
VPA
COM
BIAS
VPL
VPL
VPL
LO
24
7
23
8
ADL5387
ETC1-1-13
1000pF
22
1000pF
9
1000pF
21
10
20
11 12
19
QLO
VPB
VPB
QHI
ILO
IHI
Figure 52. ADL5387 and ADRF6510 Interfacing Example—Block Diagram
120nH
18
17
16
15
14
13
100pF
0.1µF
V POS
Rev. 0 | Page 21 of 28
As an example, a second-order Butterworth, low-pass filter design
is shown in Figure 53 where the differential load impedance is
500 Ω and the source impedance is 50 Ω. The normalized series
inductor value for the 10-to-1, load-to-source impedance ratio
is 0.074 H, and the normalized shunt capacitor is 14.814 F. For a
10.9 MHz cutoff frequency, the single-ended equivalent circuit
consists of a 0.54 μH series inductor followed by a 433 pF shunt
capacitor.
The balanced configuration is realized as the 0.54 μH inductor
is split in half to achieve the network that is shown in Figure 53.
V
V
V
S
S
S
Figure 53. Second-Order Butterworth, Low-Pass Filter Design Example
R
R
S
L
VPSD
VPS
= 0.1Ω
0.1µF
0.1µF
VPS
R
R
R
R
2
2
S
S
S
S
= 50Ω
= 50Ω
= 25Ω
= 25Ω
VPSD
COMD
LE
CLK
DATA
SDO
COM
VPS
R2
VPS
VPS
0.1µF
CONFIGURATION
CONFIGURATION
ADRF6510
DENORMALIZED
SINGLE-ENDED
SINGLE-ENDED
NORMALIZED
EQUIVALENT
L
BALANCED
N
0.54µH
0.27µH
0.27µH
= 0.074H
VOCM
OPM1
OPM2
OPP1
OPP2
GAIN
VPS
VPS
COM
COM
C
N
14.814F
433pF
433pF
0.1µF
0.1µF
VPS
0.1µF
VPS
ADRF6510
f
C
f
R
0.1µF
R
R
C
R
2
2
= 10.9MHz
L
L
L
L
= 1Hz
= 500Ω
= 500Ω
= 250Ω
= 250Ω