ADL5202XCPZ-R7 Analog Devices Inc, ADL5202XCPZ-R7 Datasheet - Page 8

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ADL5202XCPZ-R7

Manufacturer Part Number
ADL5202XCPZ-R7
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADL5202XCPZ-R7

Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
ADL5202
Pin No.
17
19, 21
20, 22
23, 24, 25,
26, 27, 28,
29, 31
30, 32
34
35
36
37
38
39
40
1
Exposed Paddle
Mnemonic
PWUPB
VOUTB+
VOUTB−
VPOS
VOUTA+
VOUTA−
PWUPA
VINA+
VINA−
LATCHA
UPDN_DAT_A/A0
UPDN_CLK_A/A1
GS0 FA_B/B2
Description
Channel B power up. A logic high on this pin enables the part.
Channel B positive output.
Channel B negative output.
Positive power supply.
Channel A positive output
Channel A negative output
Channel A power up. A logic high on this pin enables the part.
Channel A positive input.
Channel A negative input.
Latch, a low input results in gain change. A high input results in no gain change.
Multi function pin: this pin is the data pin for channel A UPDN function. In parallel mode this is bit 0 for
channel A gain interface.
Multi function pin: this pin is the clock interface for channel A UPDN function. In Parallel mode this pin is
bit1 for channel A gain interface.
Multi function pin: When the UP/DOWN mode is enabled, this pin is the LSB for the gain step size control.
A logic high enables the channel A SPI port fast attack mode. In parallel mode this pin is bit 2 for channel
A gain interface.
Rev. PrE | Page 8 of 13
Preliminary Technical Data

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