ADL5202XCPZ-R7 Analog Devices Inc, ADL5202XCPZ-R7 Datasheet

ADL5202XCPZ-R7

Manufacturer Part Number

ADL5202XCPZ-R7

Description

Manufacturer

Analog Devices Inc

Datasheet

1.ADL5202XCPZ-R7.pdf (13 pages)

Specifications of ADL5202XCPZ-R7

Operating Temperature (min)

-40C

Operating Temperature (max)

85C

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Lead Free Status / RoHS Status

Compliant

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Preliminary Technical Data

FEATURES

Dual independent digitally controlled VGAs

−11.5 to 20 dB Gain Range

0.5 dB step size ±0.1 dB

150 Ω differential input and output

6 dB noise figure @ maximum gain

OIP3 of 50 dBm at 200 MHz

−3 dB bandwidth of 700 MHz

Multiple control interface options

Wide input dynamic range

High performance power mode

Power-down control

Single 5 V supply operation

40-Lead LFCSP 6 x 6 mm package

APPLICATIONS

Differential ADC drivers

High IF sampling receivers

High output power IF amplification

Instrumentation

GENERAL DESCRIPTION

The ADL5202 is a digitally controlled, variable gain wide

bandwidth amplifier that provides precise gain control, high IP3

and low noise figure. The excellent distortion performance and

high signal bandwidth makes the ADL5202 an excellent gain

control device for a variety of receiver applications.

For wide input dynamic range applications, the ADL5202 pro-

vides a broad 31.5 dB gain range with 0.5 dB resolution. The

gain is adjustable through multiple gain control interface options:

parallel, serial peripheral interface, or gain step up/down.

Using a high speed SiGe process and incorporating proprietary

distortion cancellation techniques, the ADL5202 achieves better

than 50 dBm output IP3 at frequencies approaching 200 MHz

for all gain settings. The ADL5202 is powered on by applying

Rev. PrE

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

Parallel 6-bit control interface

Serial peripheral interface

Gain step up/down interface

31.5 dB Range, 0.5 dB Step Size

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

the appropriate logic level to the PWUP pin. The quiescent

current of the ADL5202 is typically 160 mA. It may be

configured for higher quiescent current of 220 mA, in high

performance power mode, for more demanding applications.

When powered down, the ADL5202 consumes less than 18 mA

and offers excellent input to output isolation. The gain setting is

preserved when powered down.

Fabricated on an ADI’s high speed SiGe process, the ADL5202

provides precise gain adjustment capabilities with good distortion

performance. The ADL5202 amplifier comes in a compact,

thermally enhanced 6 x 6mm 40-lead LFCSP package and

operates over the temperature range of −40°C to +85°C

VINB–

VINB+

VINA+

VINA–

FUNCTIONAL BLOCK DIAGRAM

SERIAL/PARALLEL/UP-DOWN

INTERFACE & DECODE

SERIAL/PARALLEL/UP-DOWN

INTERFACE & DECODE

UP/DOWN INTERFACE

PARALLEL, SERIAL,

0 ->31.5 dB

Programmable VGA

ADL5202

Figure 1.

VCC GND

+20 dB

PWU

ADL5202

PWUPA

www.analog.com

UPA

VOUTA+

VOUTA–

VOUTB–

VOUTB+

VOUTB–

Related parts for ADL5202XCPZ-R7

ADL5202XCPZ-R7 Summary of contents

Page 1

Preliminary Technical Data FEATURES Dual independent digitally controlled VGAs −11 Gain Range 0.5 dB step size ±0.1 dB 150 Ω differential input and output 6 dB noise figure @ maximum gain OIP3 of 50 dBm at 200 ...

Page 2

ADL5202 TABLE OF CONTENTS Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 ...

Page 3

Preliminary Technical Data SPECIFICATIONS 25° 150Ω at 100MHz p-p differential output unless otherwise noted Table 1. Parameter DYNAMIC PERFORMANCE −3 dB ...

Page 4

ADL5202 Parameter 70 MHz [Nominal Power Mode] Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point NOISE/HARMONIC PERFORMANCE 140 MHz [High Performance Power Mode] Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression ...

Page 5

Preliminary Technical Data Parameter NOISE/HARMONIC PERFORMANCE 300 MHz [High Performance Power Mode] Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 300 MHz [Nominal Power Mode] Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 ...

Page 6

ADL5202 ABSOLUTE MAXIMUM RATINGS Table Summary Table 2. Parameter Supply Voltage, V POS PWUP, Digital Pins Input Voltage IN+ IN- Internal Power Dissipation θ (Exposed paddle soldered down) JA θ (Exposed paddle not soldered down) JA θ (At ...

Page 7

Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CSA/A3 Multi function pin: When Serial mode is enabled, a logic low on this pin selects Channel A. In Parallel mode, this ...

Page 8

ADL5202 Pin No. Mnemonic Description 17 PWUPB Channel B power up. A logic high on this pin enables the part. 19, 21 VOUTB+ Channel B positive output. 20, 22 VOUTB− Channel B negative output. 23, 24, 25, VPOS Positive power ...

Page 9

Preliminary Technical Data DIGITAL INTERFACE OVERVIEW The ADL5202 DVGA has three digital control interface options: • Parallel Control Interface • Serial Peripheral Interface • Gain Step Up/Down Interface The digital control interface selection is made via 2 digital pins, MODE1 ...

Page 10

ADL5202 TYPICAL PERFORMANCE CHARACTERISTICS +20dB 0dB – 11.5dB OUT PER TONE (dBm) Figure 5. OIP3 vs. Power @ 5 Gains 25 20 ...

Page 11

Preliminary Technical Data EVALUATION BOARD The ADL5202 evaluation board is available with software control to program the variable gain control 4-layer board with split ground plane for analog and digital sections. Special care is taken to place ...

Page 12

ADL5202 VPOS R67 VXA C36 L1 L3 0.1UF 1UH 1UH NEG VOUTA1N 150 OHM DIFF PAIR POS VOUTA1P VPOS R68 VXB C37 L2 L4 C39 0.1UF 0.1UF 1UH 1UH NEG VOUTB1N 150 OHM DIFF PAIR POS VOUTB1P C38 0.1UF R73 ...

Page 13

... PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 ADL5202XCPZ-R7 −40°C to +85°C 1 ADL5202XCPZ-WP −40°C to +85°C 1 ADL5202-EVALZ −40°C to +85° RoHS Compliant Part ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...

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