ADL5202XCPZ-R7 Analog Devices Inc, ADL5202XCPZ-R7 Datasheet - Page 7

• Manufacturer Part Number: ADL5202XCPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of ADL5202XCPZ-R7

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7, 18, 33,
EP
8
9
10
11
12
13
14
15
16
1
Mnemonic
CSA/A3
A4
A5
MODE1
MODE0
PM
GND
SDIO/B5
SCLK/B4
GS1/ CSB /B3
GS0 FA_B/B2
UPDN_CLK_B/B1
UPDN_DAT_B/B0
LATCHB
VINB−
VINB+
Description
Multi function pin: When Serial mode is enabled, a logic low on this pin selects Channel A. In Parallel
mode, this bit 3 for the gain control interface.
Bit 4 for channel A parallel gain control interface.
Bit 5, (MSB) for channel A parallel gain control interface.
MSB for the mode control parallel, SPI, up/down interface.
LSB for the mode control parallel, SPI, up/down interface.
A logic low on this pin enables high performance mode. A logic high enables nominal performance
mode.
Ground
Multi function pin: When CSA or CSB is pulled low, SDIO is used for reading and writing to the SPI port. In
parallel mode, This bit is 5 (MSB) for the channel B parallel gain control interface.
Multi function pin: When SPI mode is selected this pin is the serial clock input. In parallel mode this pin is
bit 4 for channel B gain interface.
Multi function pin: When the UP/DOWN mode is enabled, this pin is the MSB for the gain step size control.
When serial mode is enabled, a logic low on this pin selects channel B. In parallel mode, this is bit 3 of the
gain control interface.
Multi function pin: When the UP/DOWN mode is enabled, this pin is the LSB for the gain step size control.
A logic high enables the channel B SPI port fast attack mode. In parallel mode this pin is bit 2 for channel
B gain interface.
Multi function pin: this pin is the clock interface for channel B UPDN function. In Parallel mode this pin is
bit1 for channel B gain interface.
Multi function pin: this pin is the data pin for channel B UPDN function. In parallel mode this is bit 0 for
channel B gain interface.
Latch, a low input results in gain change. A high input results in no gain change.
Channel B negative input.
Channel B positive input.
NC = NO CONNECT
GS1/CSB/B3
SCLK/B4
SIDO/B5
CSA/A3
MODE1
MODE0
GND
PM
A4
A5
10
1
2
3
4
5
6
7
8
9
Figure 2. 40 Lead LFCSP
Rev. PrE | Page 7 of 13
PIN 1
INDICATOR
EXPOSED PADDLE
(Not to Scale)
TOP VIEW
ADL5202
30
29
28 VPOS
27 VPOS
26 VPOS
25 VPOS
24 VPOS
23 VPOS
22
21
VOUTA–
VOUTA+
VOUTB–
VOUTB+
ADL5202