LFE2M50E-5F484C LATTICE SEMICONDUCTOR, LFE2M50E-5F484C Datasheet - Page 333
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LFE2M50E-5F484C
Manufacturer Part Number
LFE2M50E-5F484C
Description
FPGA LatticeECP2M Family 48000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M50E-5F484C
Package
484FBGA
Family Name
LatticeECP2M
Device Logic Units
48000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
270
Ram Bits
4246528
In System Programmability
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M50E-5F484C
Manufacturer:
LATTICE
Quantity:
301
Company:
Part Number:
LFE2M50E-5F484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Pinout Information
Lattice Semiconductor
LatticeECP2/M Family Data Sheet
LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)
LFE2M100E/SE
Ball Number
Ball/Pad Function
Bank
Dual Function
Differential
V18
VCCPLL
-
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
*** These sysCONFIG pins are dedicated I/O pins for configuration. The outpus are actively driven during normal device operation.
****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
4-230
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