PCA9534D,112 NXP Semiconductors, PCA9534D,112 Datasheet

PCA9534D,112

Manufacturer Part Number
PCA9534D,112
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9534D,112

Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
SO
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant
1. General description
2. Features
The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel
Input/Output (GPIO) expansion for I
enhance the NXP Semiconductors family of I
include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O
configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a
simple solution when additional I/O is needed for ACPI power switches, sensors,
push buttons, LEDs, fans, etc.
The PCA9534 consists of an 8-bit Configuration register (Input or Output selection); 8-bit
Input register, 8-bit Output register and an 8-bit Polarity Inversion register (active HIGH or
active LOW operation). The system master can enable the I/Os as either inputs or outputs
by writing to the I/O configuration bits. The data for each input or output is kept in the
corresponding Input or Output register. The polarity of the Input Port register can be
inverted with the Polarity Inversion register. All registers can be read by the system
master. Although pin-to-pin and I
software changes are required due to the enhancements and are discussed in Application
Note AN469 .
The PCA9534 is identical to the PCA9554 except for the removal of the internal I/O pull-up
resistor which greatly reduces power consumption when the I/Os are held LOW.
The PCA9534 open-drain interrupt output is activated when any input state differs from its
corresponding input port register state and is used to indicate to the system master that
an input state has changed. The power-on reset sets the registers to their default values
and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I
devices to share the same I
I
I
I
I
I
I
I
I
I
PCA9534
8-bit I
Rev. 03 — 6 November 2006
8-bit I
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
Polarity Inversion register
Active LOW interrupt output
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
2
C-bus GPIO
2
C-bus and SMBus low power I/O port with interrupt
2
C-bus/SMBus.
2
C-bus address compatible with the PCF8574 series,
2
C-bus/SMBus applications and was developed to
2
C-bus I/O expanders. The improvements
2
C-bus address and allow up to eight
Product data sheet

Related parts for PCA9534D,112

PCA9534D,112 Summary of contents

Page 1

... The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I enhance the NXP Semiconductors family of I include higher drive capability I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc ...

Page 2

... NXP Semiconductors I 8 I/O pins which default to 8 inputs 400 kHz clock frequency I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Offered in four different packages: SO16, TSSOP16, and HVQFN16 (4 and 3 3 ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning IO0 IO1 IO2 IO3 V Fig 2. Pin configuration for SO16 terminal 1 index area Fig 4. Pin configuration for HVQFN16 5.2 Pin description Table 2. Symbol IO0 IO1 IO2 IO3 V SS IO4 IO5 PCA9534_3 Product data sheet ...

Page 4

... NXP Semiconductors Table 2. Symbol IO6 IO7 INT SCL SDA V DD [1] HVQFN package die supply ground is connected to both V connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...

Page 5

... NXP Semiconductors Table 4. Bit 6.1.3 Register 1 - Output Port register This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, not the actual pin value ...

Page 6

... NXP Semiconductors 6.1.5 Register 3 - Configuration register This register configures the directions of the I/O pins bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are confi ...

Page 7

... NXP Semiconductors data from shift register configuration register data from D shift register FF write configuration CK pulse write pulse read pulse data from shift register write polarity pulse Remark: At power-on reset, all registers return to default values. Fig 6. Simplified schematic of IO0 to IO7 6.5 Device address Fig 7 ...

Page 8

... NXP Semiconductors SCL slave address SDA START condition write to port data out from port Fig 8. Write to Output Port register SCL slave address SDA START condition data to register Fig 9. Write to Configuration register or Polarity Inversion register slave address SDA START condition acknowledge ...

Page 9

... NXP Semiconductors SCL slave address SDA START condition read from port data into port t v(INT_N) INT This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition. Fig 11. Read Input Port register ...

Page 10

... NXP Semiconductors 7. Application design-in information MASTER CONTROLLER SCL SDA INT V SS Device address configured as 0100 100X for this example. IO0, IO1, IO2 configured as outputs. IO3, IO4, IO5 configured as inputs. IO6, IO7 are not used and must be configured as outputs. ...

Page 11

... NXP Semiconductors Fig 13. High value resistor in parallel with 8. Limiting values Table 8. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol I/O I O(IOn tot T stg T amb PCA9534_3 Product data sheet 2 8-bit I C-bus and SMBus low power I/O port with interrupt ...

Page 12

... NXP Semiconductors 9. Static characteristics Table 9. Static characteristics Symbol Parameter Supplies V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I leakage current ...

Page 13

... NXP Semiconductors [1] V must be lowered to 0 order to reset part. DD [2] Each I/O must be externally limited to a maximum and the device must be limited to a maximum current of 100 mA. [3] The total current sourced by all I/Os must be limited to 85 mA. 10. Dynamic characteristics Table 10. ...

Page 14

... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 15. Definition of timing START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer Fig 16. I C-bus timing diagram PCA9534_3 Product data sheet 2 8-bit I C-bus and SMBus low power I/O port with interrupt ...

Page 15

... NXP Semiconductors 11. Test information Fig 17. Test circuitry for switching times Fig 18. Test circuit Table 11. Test t v(Q) PCA9534_3 Product data sheet 2 8-bit I C-bus and SMBus low power I/O port with interrupt V I PULSE GENERATOR R = load resistor load capacitance includes jig and probe capacitance. ...

Page 16

... NXP Semiconductors 12. Package outline SO16: plastic small outline package; 16 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 17

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 18

... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 19

... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 20

... NXP Semiconductors 13. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 14. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” ...

Page 21

... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 14.4 Reflow soldering Key characteristics in reflow soldering are: • ...

Page 22

... NXP Semiconductors Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 14. Acronym ACPI CDM DUT ESD FET GPIO HBM 2 I C-bus I/O LED ...

Page 23

... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • pin names I/O0 through I/O7 changed to IO0 through IO7 • ...

Page 24

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 25

... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Registers 6.1.1 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.1.2 Register 0 - Input Port register . . . . . . . . . . . . . 4 6.1.3 Register 1 - Output Port register 6.1.4 Register 2 - Polarity Inversion register . . . . . . . 5 6.1.5 Register 3 - Confi ...

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