USB2504A-JT Standard Microsystems (SMSC), USB2504A-JT Datasheet - Page 27

• Manufacturer Part Number: USB2504A-JT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB2504A-JT

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: TQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Integrated USB 2.0 Compatible 4-Port Hub
Datasheet
SMSC USB2504/USB2504A
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
ADDR
REG
0Ah
0Bh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Slave Device Time-Out
According to the SMBus Specification, V1.0 devices in a transfer can abort the transfer in progress
and release the bus when any single clock low interval exceeds 25ms (T
have detected this condition must reset their communication and be able to receive a new START
condition no later than 35ms (T
Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically
Stretching the SCLK Signal
The Hub supports stretching of the SCLK by other devices on the SMBus. The Hub does not stretch
the SCLK.
SMBus Timing
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing
in the “Timing Diagram” section.
Bus Reset Sequence
The SMBus Slave Interface resets and returns to the idle state upon a START field followed
immediately by a STOP field.
SMBus Alert Response Address
The SMBALERT# signal is not supported by the Hub.
Internal SMBus Memory Register Set
The following table provides the SMBus slave interface register map values.
Status/Command
VID LSB
VID MSB
PID LSB
PID MSB
DID LSB
DID MSB
Config Data Byte 1
Config Data Byte 2
Non-Removable
Devices
Port Disable (Self)
Port Disable (Bus)
REGISTER NAME
resets its communications port after a start or stop condition.
Table 5.4 SMBus Slave Interface Register Map
STCD
CFG1
CFG2
ABBR
VIDM
PIDM
DIDM
VIDL
PIDL
DIDL
NRD
PDS
PDB
TIMEOUT, MAX
DATASHEET
(MSB)
BIT 7
7
7
7
7
7
7
7
7
7
7
7
7
27
).
BIT 6
6
6
6
6
6
6
6
6
6
6
6
6
BIT 5
5
5
5
5
5
5
5
5
5
5
5
5
BIT 4
4
4
4
4
4
4
4
4
4
4
4
4
BIT 3
3
3
3
3
3
3
3
3
3
3
3
3
TIMEOUT, MIN
BIT 2
2
2
2
2
2
2
2
2
2
2
2
2
Revision 2.3 (08-27-07)
). Devices that
BIT 1
1
1
1
1
1
1
1
1
1
1
1
1
BIT 0
(LSB)
0
0
0
0
0
0
0
0
0
0
0
0