JL198SGA National Semiconductor, JL198SGA Datasheet - Page 11
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JL198SGA
Manufacturer Part Number
JL198SGA
Description
Manufacturer
National Semiconductor
Datasheet
1.JL198SGA.pdf
(17 pages)
Specifications of JL198SGA
Number Of Sample And Hold Elements
1
Power Supply Requirement
Dual
Single Supply Voltage (typ)
Not RequiredV
Single Supply Voltage (min)
Not RequiredV
Single Supply Voltage (max)
Not RequiredV
Mounting
Through Hole
Lead Free Status / RoHS Status
Not Compliant
Application Hints
logic input for signal delay, calculate the slope of the wave-
form at the threshold point to ensure that it is at least
1.0 V/µs.
SAMPLING DYNAMIC SIGNALS
Sample error to moving input signals probably causes more
confusion among sample-and-hold users than any other pa-
rameter. The primary reason for this is that many users make
the assumption that the sample and hold amplifier is truly
locked on to the input signal while in the sample mode. In
actuality, there are finite phase delays through the circuit
creating an input-output differential for fast moving signals.
In addition, although the output may have settled, the hold
capacitor has an additional lag due to the 300Ω series
resistor on the chip. This means that at the moment the
“hold” command arrives, the hold capacitor voltage may be
somewhat different than the actual analog input. The effect
of these delays is opposite to the effect created by delays in
the logic which switches the circuit from sample to hold. For
example, consider an analog input of 20 Vp-p at 10 kHz.
Maximum dV/dt is 0.6 V/µs. With no analog phase delay and
100 ns logic delay, one could expect up to (0.1 µs) (0.6V/µs)
= 60 mVerror if the “hold” signal arrived near maximum dV/dt
of the input. A positive-going input would give a +60 mV
error. Now assume a 1 MHz (3 dB) bandwidth for the overall
analog loop. This generates a phase delay of 160 ns. If the
hold capacitor sees this exact delay, then error due to analog
delay will be (0.16 µs) (0.6 V/µs) = −96 mV. Total output error
is +60 mV (digital) −96 mV (analog) for a total of −36 mV. To
add to the confusion, analog delay is proportioned to hold
capacitor value while digital delay remains constant. A family
of curves (dynamic sampling error) is included to help esti-
mate errors.
A curve labeled Aperture Time has been included for sam-
pling conditions where the input is steady during the sam-
pling period, but may experience a sudden change nearly
coincident with the “hold” command. This curve is based on
a 1 mV error fed into the output.
(Continued)
11
A second curve, Hold Settling Time indicates the time re-
quired for the output to settle to 1 mV after the “hold”
command.
DIGITAL FEEDTHROUGH
Fast rise time logic signals can cause hold errors by feeding
externally into the analog input at the same time the amplifier
is put into the hold mode. To minimize this problem, board
layout should keep logic lines as far as possible from the
analog input and the C
also be used around the input line, especially if it is driven
from a high impedance source. Reducing high amplitude
logic signals to 2.5V will also help.
Use 10-pin layout. Guard around C
Guarding Technique
h
pin. Grounded guarding traces may
h
is tied to output.
20128105
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