JL198SGA National Semiconductor, JL198SGA Datasheet - Page 10

• Manufacturer Part Number: JL198SGA
• Manufacturer: National Semiconductor

Specifications of JL198SGA

• Number Of Sample And Hold Elements: 1
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Not Compliant

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Logic Input Configurations
CMOS
7V ≤ V
Threshold = 0.6 (V
Op Amp Drive
Threshold ≈ +4V
Application Hints
HOLD CAPACITOR
Hold step, acquisition time, and droop rate are the major
trade-offs in the selection of a hold capacitor value. Size and
cost may also become important for larger values. Use of the
curves included with this data sheet should be helpful in
selecting a reasonable value of capacitance. Keep in mind
that for fast repetition rates or tracking fast signals, the
capacitor drive currents may cause a significant temperature
rise in the LF198.
A significant source of error in an accurate sample and hold
circuit is dielectric absorption in the hold capacitor. A mylar
cap, for instance, may “sag back” up to 0.2% after a quick
change in voltage. A long sample time is required before the
circuit can be put back into the hold mode with this type of
capacitor. Dielectrics with very low hysteresis are polysty-
rene, polypropylene, and Teflon. Other types such as mica
and polycarbonate are not nearly as good. The advantage of
polypropylene over polystyrene is that it extends the maxi-
mum ambient temperature from 85˚C to 100˚C. Most ce-
ramic capacitors are unusable with
ramic “NPO” or “COG” capacitors are now available for
125˚C operation and also have low dielectric absorption. For
more exact data, see the curve Dielectric Absorption Error.
LOGIC
(Hi State) ≤ 15V
+
) + 1.4V
>
1% hysteresis. Ce-
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(Continued)
10
Threshold = 0.6 (V
Threshold = −4V
The hysteresis numbers on the curve are final values, taken
after full relaxation. The hysteresis error can be significantly
reduced if the output of the LF198 is digitized quickly after
the hold mode is initiated. The hysteresis relaxation time
constant in polypropylene, for instance, is 10 — 50 ms. If
A-to-D conversion can be made within 1 ms, hysteresis error
will be reduced by a factor of ten.
DC AND AC ZEROING
DC zeroing is accomplished by connecting the offset adjust
pin to the wiper of a 1 kΩ potentiometer which has one end
tied to V
The resistor should be selected to give ≈0.6 mA through the
1k potentiometer.
AC zeroing (hold step zeroing) can be obtained by adding an
inverter with the adjustment pot tied input to output. A 10 pF
capacitor from the wiper to the hold capacitor will give
hold step adjustment with a 0.01 µF hold capacitor and 5V
logic supply. For larger logic swings, a smaller capacitor
(
LOGIC RISE TIME
For proper operation, logic signals into the LF198 must have
a minimum dV/dt of 1.0 V/µs. Slower signals will cause
excessive hold step. If a R/C network is used in front of the
<
10 pF) may be used.
+
and the other end tied through a resistor to ground.
+
) − 1.4V
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±
4 mV