UDA1343TT NXP Semiconductors, UDA1343TT Datasheet - Page 8

• Manufacturer Part Number: UDA1343TT
• Manufacturer: NXP Semiconductors

Specifications of UDA1343TT

• Single Supply Voltage (typ): 3V
• Single Supply Voltage (min): 2.4V
• Single Supply Voltage (max): 3.6V
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Table 1 Application modes using input gain stage
Decimation filter (ADC)
The decimation from 64f
The first stage realizes a 4th-order
This filter decreases the sample rate by 16. The second
stage consists of 2 half-band filters and a recursive filter,
each decimating by a factor of 2.
Table 2 Digital decimation filter characteristics
In the ADC path there is a volume control with a range of
0 dB to 66 dB and
roll-off soft mute.
Note: the digital output level is inversely proportional to the
ADC analog power supply. This means that with a
constant analog input level and increasing analog power
supply, the digital output level will decrease proportionally.
Overload detection (ADC)
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is larger than
possible digital swing. When this condition is detected the
OVERFL output (pin 9) is forced HIGH for at least 512f
cycles (11.6 ms at f
each infringement.
Interpolation filter (DAC)
The digital filter interpolates from 1 to 128f
cascade of a recursive filter and an FIR filter.
2001 Jul 25
Present
Present
Absent
Absent
Pass-band ripple
Stop band
Dynamic range
Overall gain with
0 dB input to the
ADC
1 dB (the actual figure is 1.16 dB) of the maximum
Economy audio CODEC with features
RESISTOR
(12 k )
ITEM
s
= 44.1 kHz). This time-out is reset for
CONDITIONS
PGA GAIN
dB in 0.25 dB steps, and a cosine
s
0
0
to 1f
>0.55f
0 dB
6 dB
0 dB
6 dB
DC
0.45f
0.45f
s
is performed in two stages.
s
s
s
sin x
----------- -
x
characteristic.
0.5 V (RMS)
VALUE (dB)
s
MAXIMUM
2 V (RMS)
1 V (RMS)
1 V (RMS)
VOLTAGE
by means of a
INPUT
114
0.05
1.16
50
s
8
Table 3 Digital interpolation filter characteristics
Digital silence detector
The UDA1343 is equipped with a digital silence detector
on the digital data input. This detects whether a certain
amount of consecutive samples are 0. The status of the
digital silence detector can be read from the
microcontroller interface.
The number of samples can be set via the L3 interface to
3200, 4800, 9600 or 19600 samples.
The digital silence detection status can be read from the
microcontroller interface.
Mute
Muting the DAC will result in a cosine roll-off soft mute,
using 32
cosine roll-off curve is illustrated in Fig.3.
Pass-band ripple
Stop band
Dynamic range
Gain
handbook, halfpage
Fig.3 Mute as a function of raised cosine roll-off.
factor
mute
ITEM
0.8
0.6
0.4
0.2
1
0
0
4 = 128 samples (at 44.1 kHz this is 3 ms). The
CONDITIONS
1
0
0
>0.55f
DC
0.45f
0.45f
s
s
s
2
UDA1343TT
Product specification
t (ms)
VALUE (dB)
MGS755
116.5
0.03
3.5
65
3