AD73460BB-40 Analog Devices Inc, AD73460BB-40 Datasheet - Page 8

• Manufacturer Part Number: AD73460BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73460BB-40

• Analog Front End Type: General Purpose
• Analog Front End Category: General Purpose
• Interface Type: Digital
• Sample Rate: 64KSPS
• Input Voltage Range: 0.822V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 16b
• Supply Current: 54mA
• Number Of Adc's: 6
• Power Supply Type: Analog/Digital
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 119
• Package Type: BGA
• Number Of Channels: 6
• Lead Free Status / RoHS Status: Not Compliant

AD73460
Mnemonic
VINP1
VINN1
VINP2
VINN2
VINP3
VINN3
VINP4
VINN4
VINP5
VINN5
VINP6
VINN6
REFOUT
REFCAP
AVDD
AGND
DGND
DVDD
ARESET
SCLK2
MCLK
SDO
SDOFS
SDIFS
SDI
SE
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
Function
Analog Input to the Positive Terminal of Input Channel 1
Analog Input to the Negative Terminal of Input Channel 1
Analog Input to the Positive Terminal of Input Channel 2
Analog Input to the Negative Terminal of Input Channel 2
Analog Input to the Positive Terminal of Input Channel 3
Analog Input to the Negative Terminal of Input Channel 3
Analog Input to the Positive Terminal of Input Channel 4
Analog Input to the Negative Terminal of Input Channel 4
Analog Input to the Positive Terminal of Input Channel 5
Analog Input to the Negative Terminal of Input Channel 5
Analog Input to the Positive Terminal of Input Channel 6
Analog Input to the Negative Terminal of Input Channel 6
Buffered Reference Output, which has a nominal value of 1.25 V
A bypass capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed
to this pin. This pin can be overdriven by an external reference if required.
Analog Power Supply Connection
Analog Ground/Substrate Connection
Digital Ground/Substrate Connection
Digital Power Supply Connection
Active Low Reset Signal. This input resets the analog front end of the AD73460, resetting the control registers and
clearing the digital circuitry.
Output Serial Clock whose Rate Determines the Serial Transfer Rate to/from the AFE. It is used to clock data or
control information to and from the serial port (SPORT2). The frequency of SCLK is equal to the frequency
of the master clock (MCLK) divided by an integer number—this integer number being the product of the
external master clock rate divider and the serial clock rate divider.
Master Clock Input of the Analog Front End. MCLK is driven from an external clock signal.
Serial Data Output of the AD73460. Both data and control information may be output on this pin and are clocked
on the positive edge of SCLK2. SDO is in three-state when no information is being transmitted and when SE is low.
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK period
before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK2. SDOFS is in
three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK period before
the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK2 and is ignored when
SE is low.
Serial Data Input of the AD73460. Both data and control information may be input on this pin and are clocked on
the negative edge of SCLK2. SDI is ignored when SE is low.
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins
of the SPORT are three-stated and the input pins are ignored. SCLK2 is also disabled internally in order to
decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are
at their original values (before SE was brought low); however, the timing counters and other internal registers are
at their reset values.
(Input) Processor Reset Input
(Input) Bus Request Input
(Output) Bus Grant Output
(Output) Bus Grant Hung Output
(Output) Data Memory Select Output
(Output) Program Memory Select Output
(Output) Memory Select Output
(Output) Byte Memory Select Output
(Output) Combined Memory Select Output
(Output) Memory Read Enable Output
PIN FUNCTION DESCRIPTIONS
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