AD73460BB-40 Analog Devices Inc, AD73460BB-40 Datasheet - Page 16

• Manufacturer Part Number: AD73460BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73460BB-40

• Analog Front End Type: General Purpose
• Analog Front End Category: General Purpose
• Interface Type: Digital
• Sample Rate: 64KSPS
• Input Voltage Range: 0.822V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 16b
• Supply Current: 54mA
• Number Of Adc's: 6
• Power Supply Type: Analog/Digital
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 119
• Package Type: BGA
• Number Of Channels: 6
• Lead Free Status / RoHS Status: Not Compliant

AD73460
CONTROL REGISTER B
CONTROL REGISTER C
CONTROL REGISTER D
Bit
0
1
2
3
4
5
6
7
Bit
0
1
2
3
4
5
6
7
Bit
0
1
2
3
4
5
6
7
CEE
PUI2
RES
7
7
7
Name
DR0
DR1
SCD0
SCD1
MCD0
MCD1
MCD2
CEE
Name
GPU
Reserved
Reserved
Reserved
Reserved
PUREF
RU
Reserved
Name
I1GS0
I1GS1
I1GS2
PUI1
I2GS0
I2GS1
I2GS2
PUI2
Table XI. Control Register D Description
Table IX. Control Register B Description
Table X. Control Register C Description
MCD2
I2GS2
RU
6
6
6
Description
Decimation Rate (Bit 0)
Decimation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = OFF; 1 = Enabled)
Description
ADC1: Input Gain Select (Bit 0)
ADC1: Input Gain Select (Bit 1)
ADC1: Input Gain Select (Bit 2)
Power Control (ADC1): 1 = ON, 0 = OFF
ADC2: Input Gain Select (Bit 0)
ADC2: Input Gain Select (Bit 1)
ADC2: Input Gain Select (Bit 2)
Power Control (ADC2): 1 = ON, 0 = OFF
PUREF
Description
Global Power-Up Device (0 = Power Down; 1 = Power Up)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
REF Power (0 = Power Down; 1 = Power Up)
REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
Must Be Programmed to Zero (0)
MCD1
I2GS1
5
5
5
–16–
MCD0
I2GS0
RES
4
4
4
SCD1
PUI1
RES
3
3
3
SCD0
I1GS2
RES
2
2
2
I1GS1
DR1
RES
1
1
1
I1GS0
DR0
GPU
0
0
0
REV. A