AD73460BB-40 Analog Devices Inc, AD73460BB-40 Datasheet - Page 29

• Manufacturer Part Number: AD73460BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73460BB-40

• Analog Front End Type: General Purpose
• Analog Front End Category: General Purpose
• Interface Type: Digital
• Sample Rate: 64KSPS
• Input Voltage Range: 0.822V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 16b
• Supply Current: 54mA
• Number Of Adc's: 6
• Power Supply Type: Analog/Digital
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 119
• Package Type: BGA
• Number Of Channels: 6
• Lead Free Status / RoHS Status: Not Compliant

If the AD73460 is performing an external memory access when
the external device asserts the BR signal, it will not three-state
the memory interfaces nor assert the BG signal until the proces-
sor cycle after the access completes. The instruction does not
need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers, and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the AD73460 is ready to execute
an instruction, but is stopped because the external bus is already
granted to another device. The other device can release the bus by
deasserting the bus request. Once the bus is released, the AD73460
deasserts BG and BGH and executes the external memory access.
Flag I/O Pins
The AD73460 has eight general-purpose programmable input/
output flag pins. They are controlled by two memory-mapped
registers. The PFTYPE register determines the direction, 1 =
output and 0 = input. The PFDATA register is used to read and
write the values on the pins. Data being read from a pin config-
ured as an input is synchronized to the AD73460’s clock. Bits that
are programmed as outputs will read the value being output.
The PF pins default to input during reset.
In addition to the programmable flags, the AD73460 has five
fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1, and FL2.
FL0–FL2 are dedicated output flags. FLAG_IN and FLAG_OUT
are available as an alternate configuration of SPORT1.
Note: Pins PF0, PF1, PF2, and PF3 are also used for device
configuration during reset.
INSTRUCTION SET DESCRIPTION
The AD73460 assembly language instruction set has an algebraic
syntax that was designed for ease of coding and readability. The
assembly language, which takes full advantage of the processor’s
unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember cryp-
• Every instruction assembles into a single, 24-bit word that
• The syntax is a superset ADSP-2100 family assembly language
• Sixteen condition codes are available. For conditional jump,
REV. A
tic assembler mnemonics. For example, a typical arithmetic
add instruction, such as AR = AX0 + AY0, resembles a
simple equation.
can execute in a single instruction cycle.
and is completely source and object code compatible with
other family members. Programs may need to be relocated to
utilize on-chip memory and conform to the AD73460’s interrupt
vector and reset vector map.
call, return, or arithmetic instructions, the condition can
be checked and the operation executed in the same instruc-
tion cycle.
–29–
• Multifunction instructions allow parallel execution of an
DESIGNING AN EZ-ICE COMPATIBLE SYSTEM
The AD73460 has on-chip emulation support and an ICE-Port,
a special set of pins that interface to the EZ-ICE. These features
allow in-circuit emulation without replacing the target system
processor by using only a 14-pin connection from the target
system to the EZ-ICE. Target systems must have a 14-pin con-
nector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If you are using a passive method of maintaining mode
information (as discussed in Setting Memory Modes) then it
does not matter that the mode information is latched by an
emulator reset. However, if you are using the RESET pin as a
method of setting the value of the mode pins, then you have to
take into consideration the effects of an emulator reset.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 18. This circuit forces the value located on the Mode
A pin to logic high; regardless if it latched via the RESET or
ERESET pin.
The ICE-Port interface consists of the following AD73460 pins:
EBR
EMS
ELIN
These AD73460 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-down
resistors. The traces for these signals between the AD73460 and
the connector must be kept as short as possible, no longer than
three inches.
The following pins are also used by the EZ-ICE:
BR
RESET
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
EBG
EINT
ELOUT
BG
GND
Figure 18. Mode A Pin/EZ-ICE Circuit
PROGRAMMABLE I/O
ERESET
ECLK
EE
1k
ERESET
RESET
MODE A /PFO
AD73460
AD73460