LM1262NA National Semiconductor, LM1262NA Datasheet - Page 19

• Manufacturer Part Number: LM1262NA
• Manufacturer: National Semiconductor

Specifications of LM1262NA

• Power Supply Requirement: Single
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Mounting: Through Hole
• Pin Count: 24
• Package Type: MDIP
• Lead Free Status / RoHS Status: Not Compliant

DAC Interface Register Definitions
DAC 3 Register (I
Register name: DAC 3 (06h)
Bits 7–0: DAC 3. These eight bits determine the output
DAC 4 Register (I
Register name: DAC 4 (07h)
Bits 7–0: DAC 4. These eight bits determine the output
DC Offset and OSD Contrast Control Register (I
dress 08h)
Register name: DC Offset/OSD Cont. (08h)
Bits 2–0: DC Offset Control. These three bits determine the
Bits 4–3: OSD Contrast Control. These two bits determine
Bits 7–5: Reserved.
Global Video Control Register (I
Register name: Global Control (09h)
Bit 0:
Bit 1:
Bit 2:
Bit 3:
Bit 4:
Bit 5:
Bits 7–6: Reserved.
Bit 7
D3–7 D3–6 D3–5 D3–4 D3–3 D3–2 D3–1 D3–0
Bit 7
D4–7 D4–6 D4–5 D4–4 D4–3 D4–2 D4–1 D4–0
Bit 7
RSV RSV RSV OSDC1 OSDC0 DC2 DC1 DC0
(Continued)
Bit 7
RSV
RSV
voltage of DAC 3.
voltage of DAC 4.
active video DC offset to all three channels.
the contrast level of the digital OSD information.
Blank Video. When this bit is a one, blank the
video output. When this bit is a zero allow normal
video out.
Power Save. When this bit is a one, shut down
the analog circuits to support sleep mode. When
this bit is a zero enable the analog circuits for
normal operation.
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
DAC1–3 Configuration. When this bit is a zero
the DAC outputs of DAC1–3 are full scale
(0V–4.5V). When this bit is 1, the range of
DAC1–3 are halved (0V–2.25V).
DAC4 Configuration. When this bit is a zero the
DAC4 output is not mixed with the other DAC
outputs. When the bit is one, 50% of the DAC4
output is added to DAC1–3.
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
0
2
2
C address 06h)
C address 07h)
DCF4
DCF1–3
2
C address 09h)
0
PS
2
C ad-
Bit 0
Bit 0
Bit 0
Bit 0
BV
19
Increment Mode Register (I
Register name: Increment Mode (0Ah)
Bit 0:
Bit 1:
Bits 7–2: Reserved.
Clamp Polarity, Vertical Blanking, and OSD Control (I
address 0Bh)
Register name: Clamp/VBL/OOR (0Bh)
Bit 0:
Bit 1:
Bit 2:
Bit 3:
Bits 7–4: Reserved.
Software Reset Register (I
Register name: Software Reset (0Fh)
Bit 0:
Bits 7–1: Reserved.
Bit 7
RSV
Bit 7
RSV
Bit 7
RSV
RSV
RSV
RSV
Increment Enable. When set to a “0”, the default
value, the increment mode is enabled. This al-
lows the registers to be updated sequentially by
sending another block of data.
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
OSD Only Register: When this bit is 0 (default)
normal video operation is assumed. When this bit
is 1, the video is blanked, only the OSD window is
displayed (used for “out-of-range” condition).
Vertical Blank Enable: When this bit is set to 1 the
vertical blanking pulse is OR’d with the horizontal
blank pulse at the preamplifier output, to blank
the video during both the vertical and horizontal
retrace. I
only be updated during vertical retrace period.
When this bit is set to 0 (default) the internal
vertical blanking is disabled (horizontal blanking
is not affected) and I
DAC4 occur anytime in the video field. NOTE: If
there is no vertical signal to the LM1262, this bit
must be set to a 0 for proper operation.
DAC4 I/O Switch: When this bit is set to 1 (de-
fault) DAC4 output is enabled. When this bit is set
to a 0 the DAC4 output is disabled and pin 13 is
used for the vertical blank input. DAC4 can still be
connected internally to DAC1-3. When both bits 1
and 2 are set to 1 vertical blanking will be stripped
from the sandcastle pulse at pin 23. For proper
detection of the sandcastle pulse the CLMP bit
(bit 3) must be set to a 0, positive polarity for the
clamp input.
Determines the polarity of the clamp signal used
by the LM1262, “0” (default) is a positive clamp
signal, “1” is a negative going clamp signal.
Software Reset. Setting this bit causes a software
reset. All registers (except this one) are loaded
with their default values. All operations currently
in progress are aborted (except for I
tions). This bit automatically clears itself when the
reset has been completed.
RSV
RSV
RSV
2
C changes for contrast and DAC4 will
RSV
RSV
RSV
2
2
C address 0Fh)
CLMP
C address 0Ah)
RSV
2
C changes for contrast and
RSV
RSV
DAC4
RSV
RSV
VBL
2
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0
C transac-
SRST
INCR
OOR
Bit 0
Bit 0
Bit 0
2
C