LM1262NA National Semiconductor, LM1262NA Datasheet - Page 16

• Manufacturer Part Number: LM1262NA
• Manufacturer: National Semiconductor

Specifications of LM1262NA

• Power Supply Requirement: Single
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Mounting: Through Hole
• Pin Count: 24
• Package Type: MDIP
• Lead Free Status / RoHS Status: Not Compliant

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PCB Layout
Micro-Controller Interface
The micro-controller interfaces to the LM1262 pre-amp via
an I
Start Pulse followed by a byte comprised of a seven-bit
Slave Device Address and a Read/Write bit as the LSB.
Therefore the address of the LM1262 for writing is DCh
(1101 1100) and the address for reading is DDh (1101 1101).
Figures 11, 12 show a write and read sequence across the
I
Write Sequence
The write sequence begins with a start condition which
consists of the master pulling SDA low while SCL is held
high. The slave device address is next sent. The address
byte is made up of an address of seven bits (7–1) and the
read/write bit (0). Bit 0 is low to indicate a write operation.
Each byte that is sent is followed by an acknowledge. When
SCL is high the master will release the SDA line. The slave
must pull SDA low to acknowledge. The address of the
register to be written to is sent next. Following the register
address and the acknowledge bit the data for the register is
sent. If bit 0 of register 0Ah is set low (default value) then the
LM1262 is set for the increment mode. In this mode when
more than one data byte is sent it is automatically incre-
mented into the next address location. See Figure 11 . Note
that each data byte is followed by an acknowledge bit.
2
C interface.
2
C interface. The protocol of the interface begins with the
FIGURE 10. High Speed Low Cost System Neck Board
16
Read Sequence
Read sequences are comprised of two I
quences. The first is a write sequence that only transfers the
address to be accessed. The second is a read sequence that
starts at the address transferred in the previous address
write access and incrementing to the next address upon
every data byte read. This is shown in Figure 12 .
The write sequence consists of the Start Pulse, the Slave
Device Address including the Read/Write bit (a zero, indicat-
ing a write), then its Acknowledge bit. The next byte is the
address to be accessed, followed by its Acknowledge bit and
the stop bit indicating the end of the address only write
access.
Next the read data access is performed beginning with the
Start Pulse, the Slave Device Address including the Read/
Write bit (a one, indicating a read) and the Acknowledge bit.
The next 8 bits will be the data read from the address
indicated by the write sequence. Subsequent read data
bytes will correspond to the next increment address loca-
tions. Each data byte is separated from the other data bytes
by an Acknowledge bit.
2
C transfer se-
DS200404-37