MF6CWM-100 National Semiconductor, MF6CWM-100 Datasheet - Page 8

MF6CWM-100

Manufacturer Part Number
MF6CWM-100
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of MF6CWM-100

Architecture
Switched Capacitor
Dual Supply Voltage (typ)
±3/±5V
Power Supply Requirement
Single/Dual
Single Supply Voltage (min)
5V
Dual Supply Voltage (min)
±2.5V
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Package Type
SOIC W
Filter Type
Low Pass Filter
Lead Free Status / RoHS Status
Not Compliant

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Typical Performance Characteristics
DC Gain Deviation
vs Power Supply Voltage
Crosstalk Test Circuits
Pin Descriptions
Pin
FILTER OUT
(3)
FILTER IN (8)
Description
The output of the lowpass filter. It
will typically sink 0.9 mA and source
3 mA and swing to within 1V of each
supply rail.
The input to the lowpass filter. To
minimize gain errors the source
impedance that drives this input
should be less than 2k (see section
1.4). For single supply operation the
input signal must be biased to
mid-supply or AC coupled.
DS005065-64
(Pin Numbers)
From Either Op Amp to Filter Output
DC Gain Deviation
vs Clock Frequency
From Filter to Op Amps
(Continued)
8
Pin
V
OS
ADJ (7)
DS005065-65
Description
This pin is used to adjust the DC
offset of the filter output; if not used
it must be tied to the AGND
potential. (See section 1.3)
DS005065-10
DS005065-11

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