MF6CWM-100 National Semiconductor, MF6CWM-100 Datasheet - Page 14

MF6CWM-100

Manufacturer Part Number
MF6CWM-100
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of MF6CWM-100

Architecture
Switched Capacitor
Dual Supply Voltage (typ)
±3/±5V
Power Supply Requirement
Single/Dual
Single Supply Voltage (min)
5V
Dual Supply Voltage (min)
±2.5V
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Package Type
SOIC W
Filter Type
Low Pass Filter
Lead Free Status / RoHS Status
Not Compliant

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1.0 MF6 Application Hints
(where T equals one clock period) or
The equivalent input resistor (R
The input capacitor is 2 pF for the MF6-50 and 1 pF for the
MF6-100, so for the MF6-100
and
for the MF6-50. As shown in the above equations for a given
cutoff frequency (f
for the MF6-50 and the MF6-100. The higher the clock to
center frequency ratio, the greater equivalent input resis-
tance for a given clock frequency. As the cutoff frequency in-
creases the equivalent input impedance decreases. This in-
put resistance will form a voltage divider with the source
impedance (R
the cutoff frequency, operation at higher cutoff frequencies
will be more likely to load the input signal which would ap-
pear as an overall decrease in gain to the output of the filter.
Since the filter’s ideal gain is unity its overall gain is given by:
If the MF6-50 or the MF6-100 were set up for a cutoff fre-
quency of 10 kHz the input impedance would be:
In this example with a source impedance of 10k the overall
gain, if the MF6 had an ideal gain of 1 or 0 dB, would be:
Since the maximum overall gain error for the MF6 is
with a R
+0.21 dB to −0.39 dB.
1.5 CUTOFF FREQUENCY RANGE
The filter’s cutoff frequency (f
leakage currents through the internal switches discharging
the stored charge on the capacitors. At lower clock frequen-
cies these leakage currents can cause millivolts of error, for
example:
s
2 k
source
the actual gain error for this case would be
c
) the input impedance remains the same
). Since R
c
in
) has a lower limit caused by
in
is inversely proportional to
) then can be defined as
(Continued)
±
0.3 dB
14
The propagation delay in the logic and the settling time re-
quired to acquire a new voltage level on the capacitors in-
creases as the MF6 power supply voltage decreases. This
causes a shift in the f
able when the clock frequency exceeds 250 kHz. The ampli-
tude characteristic will stay within tolerance until f
ceeds 500 kHz and will peak at about 0.5 dB at the corner
frequency with a 1 MHz clock. The response of the MF6 is
still a reasonable approximation of the ideal Butterworth low-
pass characteristic as can be seen in Figures 7, 8, 9, 10 .
FIGURE 9. MF6-100
FIGURE 7. MF6-100
FIGURE 8. MF6-50
Amplitude Response
Amplitude Response
Amplitude Response
CLK
/f
c
ratio which will become notice-
±
±
±
2.5V Supplies
5V Supplies
5V Supplies
DS005065-20
DS005065-21
DS005065-22
CLK
ex-

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