ISP1506ABS,557 NXP Semiconductors, ISP1506ABS,557 Datasheet - Page 24

• Manufacturer Part Number: ISP1506ABS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1506ABS,557

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
ISP1506A_ISP1506B_2
Product data sheet
Fig 7.
DATA[3:0]
RESET_N
CLOCK
NXT
STP
DIR
Interface behavior with respect to RESET_N
9.3.2 Interface behavior with respect to RESET_N
9.4.1 Driving 5 V on V
9.4 V
Hi-Z (input)
Hi-Z (input)
The interface protect feature prevents unwanted activity of the ISP1506 whenever the
ULPI interface is not correctly driven by the link. For example, when the link powers up
more slowly than the ISP1506.
The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.
The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the
ISP1506 will assert DIR. All logic in the ISP1506 will be reset, including the analog
circuitry and ULPI registers. During reset, the link must drive DATA[3:0] and STP to LOW;
otherwise undefined behavior may result. When RESET_N is deasserted (HIGH), the DIR
output will deassert (LOW) four or five clock cycles later.
interface behavior when RESET_N is asserted (LOW), and subsequently deasserted
(HIGH). If RESET_N is not used, it must be connected to V
The ISP1506 provides a built-in charge pump. To enable the charge pump, the link must
set the DRV_VBUS bit in the OTG Control register.
The ISP1506 also supports external 5 V supplies. The ISP1506 can control the external
supply using the active-LOW PSW_N open-drain output pin. To enable the external supply
by driving PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG Control
register to logic 1. The link can optionally set both the DRV_VBUS and DRV_VBUS_EXT
bits to logic 1 to enable the external supply.
Table 8
BUS
power and fault detection
summarizes settings to drive 5 V on V
Hi-Z (link must drive)
Hi-Z (link must drive)
BUS
Rev. 02 — 28 August 2008
Hi-Z (input)
Hi-Z (input)
ISP1506A; ISP1506B
BUS
.
Figure 7
ULPI HS USB OTG transceiver
CC(I/O)
.
shows the ULPI
© NXP B.V. 2008. All rights reserved.
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