SC16C650AIB48 NXP Semiconductors, SC16C650AIB48 Datasheet - Page 7

• Manufacturer Part Number: SC16C650AIB48
• Manufacturer: NXP Semiconductors

Specifications of SC16C650AIB48

• Transmitter And Receiver Fifo Counter: Yes
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
Table 2:
9397 750 11622
Product data
Symbol
CS0, CS1,
CS2
CTS
D(7:0)
DCD
DDIS
DSR
DTR
INT
MR
OUT1, OUT2 38, 35
RCLK
Pin description
Pin
PLCC44 LQFP48 DIP40
14, 15,
16
40
2-9
42
26
41
37
33
39
10
9, 10,
11
38
43-47,
2-4
40
22
39
33
30
35
34, 31
5
…continued
12, 13,
14
36
8-1
38
23
37
33
30
35
34, 31 O
9
Type
I
I
I/O
I
O
I
O
O
I
I
Rev. 04 — 20 June 2003
Description
Chip select. When CS0 and CS1 are HIGH and CS2 is LOW, these
three inputs select the UART. When any of these inputs are inactive,
the UART remains inactive (refer to AS description).
Clear to send. CTS is a modem status signal. Its condition can be
checked by reading bit 4 (CTS) of the modem status register. Bit 0
( CTS) of the modem status register indicates that CTS has changed
states since the last read from the modem status register. If the
modem status interrupt is enabled when CTS changes levels and the
auto-CTS mode is not enabled, an interrupt is generated. CTS is also
used in the auto-CTS mode to control the transmitter.
Data bus. Eight data lines with 3-State outputs provide a bi-directional
path for data, control and status information between the UART and
the CPU.
Data carrier detect. DCD is a modem status signal. Its condition can
be checked by reading bit 7 (DCD) of the modem status register. Bit 3
( DCD) of the modem status register indicates that DCD has changed
states since the last read from the modem status register. If the
modem status interrupt is enabled when DCD changes levels, an
interrupt is generated.
Driver disable. DDIS is active (LOW) when the CPU is not reading
data. When active, DDIS can disable an external transceiver.
Data set ready. DSR is a modem status signal. Its condition can be
checked by reading bit 5 (DSR) of the modem status register. Bit 1
( DSR) of the modem status register indicates DSR has changed
levels since the last read from the modem status register. If the
modem status interrupt is enabled when DSR changes levels, an
interrupt is generated.
Data terminal ready. When active (LOW), DTR informs a modem or
data set that the UART is ready to establish communication. DTR is
placed in the active level by setting the DTR bit of the modem control
register. DTR is placed in the inactive level either as a result of a
Master Reset, during loop mode operation, or clearing the DTR bit.
Interrupt. When active (HIGH), INT informs the CPU that the UART
has an interrupt to be serviced. Four conditions that cause an interrupt
to be issued are: a receiver error, received data that is available or
timed out (FIFO mode only), an empty transmitter holding register or
an enabled modem status interrupt. INT is reset (deactivated) either
when the interrupt is serviced or as a result of a Master Reset.
Master Reset. When active (HIGH), MR clears most UART registers
and sets the levels of various output signals.
Outputs 1 and 2. These are user-designated output terminals that are
set to the active (low) level by setting respective modem control
register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to
inactive the (HIGH) level as a result of Master Reset, during loop mode
operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.
Receiver clock. RCLK is the 16 baud rate clock for the receiver
section of the UART.
UART with 32-byte FIFO and IrDA encoder/decoder
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C650A
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