SC16C850SVIBS-S NXP Semiconductors, SC16C850SVIBS-S Datasheet - Page 15

• Manufacturer Part Number: SC16C850SVIBS-S
• Manufacturer: NXP Semiconductors

Specifications of SC16C850SVIBS-S

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
9397 750 11618
Product data
6.5.1 Interrupt mode operation
6.5.2 Polled mode operation
In interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of
the receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary
to continuously poll the line status register (LSR) to see if any interrupt needs to be
serviced.
In polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be
checked by polling the line status register (LSR). This mode is an alternative to the
FIFO interrupt mode of operation where the status of the receiver and transmitter is
automatically known by means of interrupts sent to the CPU.
polled mode operation.
Fig 8. Interrupt mode operation.
Fig 9. FIFO polled mode operation.
Figure 8
PROCESSOR
PROCESSOR
shows interrupt mode operation.
Rev. 04 — 19 June 2003
IOW / IOR
IOW / IOR
INT
THR
THR
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
IIR
LSR
IER
IER
1
0
Figure 9
1
0
SC16C754
RHR
RHR
1
0
002aaa230
002aaa231
1
0
shows FIFO
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