XR17D154IV Exar Corporation, XR17D154IV Datasheet - Page 43

• Manufacturer Part Number: XR17D154IV
• Description: Universal QUART W/ PCI Bus Interface.
• Manufacturer: Exar Corporation

Specifications of XR17D154IV

• Features: *
• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

xr
REV. 1.2.2
LCR[6]: Transmit Break Enable
When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", LOW state). This condition remains until disabled by setting LCR bit-6 to a logic 0.
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•
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
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•
The MCR register is used for controlling the modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Pins
The DTR# pin may be used for automatic hardware flow control enabled by EFR bit-6 and MCR bit-2=1. If the
modem interface is not used, this output may be used for general purpose.
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•
MCR[1]: RTS# Pins
The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit-6 and MCR bit-2=0. If
the modem interface is not used, this output may be used for general purpose.
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•
MCR[2]: DTR# or RTS# for Auto Flow Control
DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by
EFR bit-6. DTR# selection is associated with DSR# and RTS# is with CTS#.
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•
MCR[3]: (OP2)
The OP2 output is not available in the XR17D154. It is present for 16C550 compatibility during internal
loopback. See
MCR[4]: Internal Loopback Enable
•
•
5.8.8
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
Logic 0 = Force RTS# output HIGH (default).
Logic 1 = Force RTS# output LOW.
Logic 0 = Uses RTS# and CTS# pins for auto hardware flow control.
Logic 1 = Uses DTR# and DSR# pins for auto hardware flow control.
Logic 0 = Disable internal loopback mode (default).
Logic 1 = Enable internal loopback mode, see loopback section and
Modem Control Register (MCR) - Read/Write
Figure 18
LCR B
. Logic 0 is default.
X
0
0
1
1
IT
-5 LCR B
X
0
1
0
1
T
ABLE
IT
-4 LCR B
16: P
0
1
1
1
1
ARITY SELECTION
IT
43
-3
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
Forced parity to space, “0”
Force parity to mark, “1”
P
ARITY SELECTION
Even parity
Odd parity
No parity
Figure 18
.
XR17D154