XR17D154IV Exar Corporation, XR17D154IV Datasheet - Page 36

• Manufacturer Part Number: XR17D154IV
• Description: Universal QUART W/ PCI Bus Interface.
• Manufacturer: Exar Corporation

Specifications of XR17D154IV

• Features: *
• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
T
A
ABLE
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 0
1 0 1 1
1 0 1 1
A3-A0
DDRESS
13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
TXTRG
RXCNT
RXTRG
TXCNT
FCTR
N
MCR
MSR
MSR
RHR
THR
DLM
FCR
SPR
R
LCR
LSR
EFR
DLL
IER
ISR
AME
EG
W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EAD
RITE
W
W
W
W
W
R
R
R
R
R
/
CTS/DSR
DSR# Int.
Prescaler
RX FIFO
RX FIFO
Enable
Enable
Trigger
Divisor
Enable
E
RS485
Enable
FIFOs
DLY-3
B
CTS/
Table
BRG
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
TRG
Auto
Bit-7
Bit-7
Bit-7
Bit-7
RROR
Bit-1
CD
IT
0/
0/
-7
DTR# Int.
RTS/DTR
RX FIFO
Enable
Enable
Trigger
Set TX
Enable
RS485
Enable
FIFOs
Empty
Break
DLY-2
B
RTS/
Table
TRG
Bit-6
Bit-6
Bit-6
Bit-6
TSR
Bit-6
Auto
Bit-6
Bit-6
Bit-6
Bit-6
Bit-0
IR
RI
IT
0/
0/
-6
Set Parity Even Par-
Xon/Xoff/
Sp. Char.
Flow Cntl
TX FIFO
XonAny
Special
Enable
Trigger
RS485
RS485
Enable
Empty
Select
Delta-
DLY-1
B
DSR
Char
Bit-5
Bit-5
Bit-5
Bit-5
THR
Bit-5
Auto
Bit-5
Bit-5
Bit-5
Bit-5
Int.
IT
0/
0/
0/
0/
-5
36
Xoff/special
MCR[7:5,2]
RX Break
FCR[5:4],
IER [7:5],
ISR [5:4],
MSR[7:4]
TX FIFO
RX Input
Lopback
Invert IR
Internal
Trigger
Enable
RS485
Enable
DLY-0
B
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
char
CTS
ity
IT
0/
0/
0
-4
Status Int.
Hyst Bit-3
RX Fram-
Reserved Reserved Reserved Reserved
RTS/DTR
Flow Cntl
Software
ing Error
Modem
Source
Enable
Enable
(OP2)
Parity
Mode
B
DMA
Delta
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
INT
IT
-3
1
Status Int.
Hyst Bit-2
RTS/DTR
RX Parity
RTS/DTR
Flow Cntl
Stop Bits
Software
TX FIFO
Flow Sel
RX Line
Enable
Source
(OP1)
Reset
B
Error
Delta
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
INT
RI#
IT
-2
S
1
HADED BITS ARE ENABLED BY
TX Empty
RTS/DTR
Hyst Bit-1
RTS# Pin
RX Over-
Flow Cntl
RX FIFO
Software
Enable
Source
Control
Length
DSR#
Reset
Word
B
Delta
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
run
Int.
IT
-1
xr
DTR# Pin
RTS/DTR
Hyst Bit-0
Flow Cntl
Software
RX Data
RX Data
Enable
Source
Enable
Control
Length
FIFOs
Ready
CTS#
B
Word
Delta
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
INT
Int.
IT
-0
REV. 1.2.2
EFR B
User Data
C
LCR[7]=0
LCR[7]=0
LCR[7]=1
LCR[7]=1
OMMENT
IT
-4.