XR17D154IV Exar Corporation, XR17D154IV Datasheet - Page 26

• Manufacturer Part Number: XR17D154IV
• Description: Universal QUART W/ PCI Bus Interface.
• Manufacturer: Exar Corporation

Specifications of XR17D154IV

• Features: *
• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation
(maximum 16 DWORD writes) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel 2),
and 0x700 (channel 3).
The THR and RHR register address for channel 0 to channel 3 is shown in
for each channel 0 to 3 are located sequentially at address 0x0000, 0x0200, 0x0400 and 0x0600. Transmit
data byte is loaded to the THR when writing to that address and receive data is unloaded from the RHR
register when reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so
each bus operation can only write or read in bytes.
4.2
4.1.3
Write n+0 to n+3
Write n+4 to n+7
W
Data Bit-31
PCI Bus
RITE
B7 B6 B5 B4 B3 B2 B1 B0
FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT
Etc.
TX FIFO
Tx FIFO Data Loading at locations 0x100, 0x300, 0x500, 0x700
Transmit Data Byte n+3
T
ABLE
CH0 0x000 Read RHR
CH2 0x400 Read RHR
CH3 0x600 Write THR
CH3 0x600 Read RHR
CH0 0x000 Write THR
CH1 0x200 Write THR
CH1 0x200 Read RHR
CH2 0x400 Write THR
9: T
THR and RHR Address Locations For CH0 to CH3 (16C550 Compatible)
RANSMIT AND
Channel 0 to 3 Transmit Data in 32-bit alignment through the Configuration Register Address
FIFO Data n+3
FIFO Data n+7
B
YTE
B7 B6 B5 B4 B3 B2 B1 B0
3
Transmit Data Byte n+2
R
ECEIVE
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
0x0100, 0x0300, 0x0500 and 0x0700
D
ATA
FIFO Data n+2
FIFO Data n+6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
R
B
EGISTER IN
YTE
26
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
2
B7 B6 B5 B4 B3 B2 B1 B0
Transmit Data Byte n+1
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
B
YTE FORMAT
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
FIFO Data n+1
FIFO Data n+5
B
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
YTE
Table 9
, 16C550
1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
B7 B6 B5 B4 B3 B2 B1 B0
below. The THR and RHR
784THRRHR1
Transmit Data Byte n+0
COMPATIBLE
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
xr
FIFO Data n+0
FIFO Data n+4
B
YTE
REV. 1.2.2
Data Bit-0
0
PCI Bus