TDA9955HL/17/C1:55 NXP Semiconductors, TDA9955HL/17/C1:55 Datasheet - Page 23

• Manufacturer Part Number: TDA9955HL/17/C1:55
• Description: TDA9955HL/LQFP100/TRAYBDP//17/
• Manufacturer: NXP Semiconductors
• Type: Videor

Specifications of TDA9955HL/17/C1:55

• Resolution (bits): 8 b
• Sampling Rate (per Second): 170M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.75 V ~ 1.85 V, 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935281545551; TDA9955HL/17/C1-S; TDA9955HL/17/C1-S

NXP Semiconductors
Table 21.
Legend: * = default value
Table 22.
Legend: * = default value
Table 23.
[1]
TDA9955HL_1
Product data sheet
Addr Register
2Ah
2Bh
2Ch
2Dh
Addr Register
34h
35h
36h
37h
Addr Register
40h
41h
44h
42h
44h
43h
44h
The recommended frequency for MCLK signal is 13.5 MHz.
COARSE_GAINBU 7 to 4 -
FINE_GAINBU
AGC_HIGHBU
AGC_LOWBU
COARSE_GAINGY 7 to 4 -
FINE_GAINGY
AGC_HIGHGY
AGC_LOWGY
V_PER_MSB
V_PER_ISB
STM_LSB
H_PER_MSB
STM_LSB
HS_WIDTH_MSB 7 to 0 HS_WIDTH[9:2] R
STM_LSB
B/U video gain registers (addresses 2Ah to 2Dh) bit description
G/Y video gain registers (addresses 34h to 37h) bit description
Sync timing measurement registers (address 40h to 44h) bit description
9.2.9 Sync timing measurement registers
Bit
7 to 0 V_PER[19:12]
7 to 0 V_PER[11:4]
7 to 4 V_PER[3:0]
7 to 0 H_PER[9:2]
3 to 2 H_PER[1:0]
1 to 0 HS_WIDTH[1:0] R
Bit
3 to 0 COARSE_GY[3:0] W
7
6 to 0 FINE_BU[6:0]
7 to 0 HIGH_BU[7:0]
7
6 to 0 LOW_BU[6:0]
Bit
3 to 0 COARSE_GY[3:0] W
7
6 to 0 FINE_GY[6:0]
7 to 0 HIGH_GY[7:0]
7
6 to 0 LOW_GY[6:0]
Symbol
Symbol
-
-
Symbol
-
-
Rev. 01 — 17 March 2008
Access Value Description
R
R
R
R
R
Access Value
W
W
W
W
W
W
Access Value Description
W
W
W
W
W
W
Triple 8-bit analog-to-digital video converter for HDTV
00h*
00h*
0000*
00h*
00*
00h*
00*
04h*
5Ch*
90h*
04h*
5Ch*
90h*
F0h*
F0h*
vertical period: indicates the period of two fields
(interlaced) or frames (progressive), counted in MCLK
clock periods
horizontal period: indicates the period of the line,
counted in MCLK clock periods
horizontal sync width: indicates the width of the
horizontal sync pulse, counted in MCLK clock
periods
not used
coarse_gy: coarse gain value for the channel
G/Y
not used
fine_gy: fine gain value for the channel G/Y
high_gy: AGC high value for the channel G/Y
not used
low_gy: AGC low value for the channel G/Y
Description
not used
coarse_bu: coarse gain value for channel B/U
not used
fine_bu: fine gain value for channel B/U
high_bu: AGC high value for channel B/U
not used
low_bu: AGC low value for channel B/U
[1]
[1]
TDA9955HL
[1]
© NXP B.V. 2008. All rights reserved.
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