TDA9955HL/17/C1:55 NXP Semiconductors, TDA9955HL/17/C1:55 Datasheet - Page 21

• Manufacturer Part Number: TDA9955HL/17/C1:55
• Description: TDA9955HL/LQFP100/TRAYBDP//17/
• Manufacturer: NXP Semiconductors
• Type: Videor

Specifications of TDA9955HL/17/C1:55

• Resolution (bits): 8 b
• Sampling Rate (per Second): 170M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.75 V ~ 1.85 V, 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935281545551; TDA9955HL/17/C1-S; TDA9955HL/17/C1-S

NXP Semiconductors
Table 16.
TDA9955HL_1
Product data sheet
MDIV[1:0] Master
11
10
01
00
Relation between master division and clock division
division
8
4
2
1
9.2.6 Pixel clocks generation registers
Table 14.
Legend: * = default value
Table 15.
Table 17.
Legend: * = default value
4 : 4 : 4 or semi-planar 4 : 2 : 2 ITU-R BT.656 formatter clock
CLKOUT
_DIV
10
01
00
11
Bit
1
0
PHASE[4:0]
0 to 7
8 to 15
16 to 31
Bit
7
6 to 4 CLKOUT_SEL[2:0] W
Symbol
CLKOUT_TOG
Symbol
PR_DEL
PH_CORR
PIXCLKGEN_CTRL0 register (address 16h) bit description
Relationship between bits PR_DEL, PH_CORR and phase value
PIXCLKGEN_CTRL1 register (address 17h) bit description
CLKOUT
_PRST
0 to 7
0 to 3
0 or 1
0
Rev. 01 — 17 March 2008
CLKOUT
_DIV
01
00
11
not available
Access Value Description
W
Access Value Description
W
W
PR_DEL
0
1
1
Triple 8-bit analog-to-digital video converter for HDTV
CLKOUT
_PRST
0, 1, 2, 3
0 or 1
0
0*
1
000
001
010
011
100*
101
110
111
0
1*
0
1*
output clock toggle
output clock selection: select the clock available
on pin VCLK
phase delay: delays the rough adjustment of the
three clock signals, see
phase correction: selects the falling or rising edge
of the horizontal reference signal from the PLL to
synchronize the three clock divisions, see
does not toggle the signal CLKOUT
reserved for test
reserved for test
not defined
not defined
CLKOUT
CLKFOR
CLKPIX
not defined
toggles the signal CLKOUT
no delay
delay of one PLL period
falling edge selected
rising edge selected
CLKFOR
_DIV
01
00
11
not available
CLKFOR
_PRST
0, 1, 2, 3
0 or 1
0
PH_CORR
0
1
0
Table 15
TDA9955HL
…continued
pixel clock
CLKPIX
_DIV
10
01
00
00
© NXP B.V. 2008. All rights reserved.
CLKPIX
_PRST
0 to 7
0 to 3
0 or 1
0
Table 15
21 of 52