SX1233IMLTRT Semtech, SX1233IMLTRT Datasheet - Page 8

RF Transceiver Extended Bands Japan-Korea

SX1233IMLTRT

Manufacturer Part Number
SX1233IMLTRT
Description
RF Transceiver Extended Bands Japan-Korea
Manufacturer
Semtech
Datasheet

Specifications of SX1233IMLTRT

Transmitting Current
95mA
Data Rate
600Kbps
Rf Ic Case Style
QFN
No. Of Pins
24
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Receiving Current
17mA

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SX1233IMLTRT
Manufacturer:
INFINEON
Quantity:
4 300
This product datasheet contains a detailed description of the SX1233 performance and functionality. Please
consult the Semtech website for the latest updates or errata.
Refer to section 9 of this document to identify chip revisions.
1. General Description
The SX1233 is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The
SX1233's advanced features set, including state of the art packet engine greatly simplifies system design whilst the high
level of integration reduces the external BOM to a handful of passive decoupling and matching components. It is intended
for use as high-performance, low-cost FSK and OOK RF transceiver for robust frequency agile, half-duplex bi-directional
RF links, and where stable and constant RF performance is required over the full operating range of the device down to
1.8V.
The SX1233 is intended for applications over a wide frequency range, including the 433 MHz and 868 MHz European and
the 902-928 MHz North American ISM bands. Coupled with a link budget in excess of 135 dB, the advanced system
features of the SX1233 include a 66 byte TX/RX FIFO, configurable automatic packet handler, listen mode, temperature
sensor and configurable DIOs which greatly enhance system flexibility whilst at the same time significantly reducing MCU
requirements.
The SX1233 complies with both ETSI and FCC regulatory requirements and is available in a 5x 5 mm QFN 24 lead
package
1.1. Simplified Block Diagram
Rev 5 - June 2011
ADVANCED COMMUNICATIONS & SENSING
PA_BOOST
VR_PA
RFIO
GND
PA1&2
PA0
Ramp &
Control
LNA
VBAT1&2
Receiver Blocks
Frequency Synthesis
Power Distribution System
Differential
Single to
VR_ANA
Inductor
Loop
Filter
Tank
Figure 1. Block Diagram
Frac-N PLL
Synthesizer
Division by
2, 4 or 6
32 MHz
Mixers
XTAL
XO
VR_DIG
Page 8
Transmitter Blocks
Control Blocks
Modulators
Σ/Δ
RSSI
GND
Oscillator
RC
AFC
Primarily Digital
Primarily Analog
SPI
RXTX
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
RESET
DATASHEET
www.semtech.com
SX1233

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