STK12C68-5L35M Cypress Semiconductor Corp, STK12C68-5L35M Datasheet - Page 5

• Manufacturer Part Number: STK12C68-5L35M
• Description: STK12C68-5L35M
• Manufacturer: Cypress Semiconductor Corp

Specifications of STK12C68-5L35M

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 64K (8K x 8)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 28-LCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the t
ready for Read and Write operations. The RECALL operation
does not alter the data in the nonvolatile elements. The nonvol-
atile data can be recalled an unlimited number of times.
Data Protection
The STK12C68-5 protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and Write operations. The low voltage condition is detected
when V
mode (both CE and WE are low) at power up after a RECALL or
after a STORE, the Write is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brown out conditions.
Noise Considerations
The STK12C68-5 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Hardware Protect
The STK12C68-5 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage condi-
tions. When V
operations and SRAM Writes are inhibited. AutoStore can be
completely disabled by tying VCC to ground and applying +5V to
V
are only initiated by explicit request using either the software
sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the STK12C68-5 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns.
between I
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK12C68-5
depends on the following items:
■
■
■
■
■
■
Document Number: 001-51026 Rev. **
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
CAP
The duty cycle of chip enable
The overall cycle rate for accesses
The ratio of Reads to Writes
CMOS versus TTL input levels
The operating temperature
The V
. This is the AutoStore Inhibit mode; in this mode, STOREs
CC
CC
CC
is less than V
CC
level
and Read or Write cycle time. Worst case current
and V
Figure 5
CAP
<V
SS,
SWITCH
using leads and traces that are as short
RECALL
SWITCH
and
, all externally initiated STORE
Figure 6
. If the STK12C68-5 is in a Write
cycle time, the SRAM is again
shows the relationship
Figure 5. Current Versus Cycle Time (Read)
Figure 6. Current Versus Cycle Time (Write)
Preventing Store
The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a V
because it must overpower the internal pull down device. This
device drives HSB LOW for 20 μs at the onset of a STORE.
When the STK12C68-5 is connected for AutoStore operation
(system V
and V
attempts to pull HSB LOW. If HSB does not actually get below
V
attempt.
IL
, the part stops trying to pull HSB LOW and abort the STORE
CC
crosses V
CC
STK12C68-5 (SMD5962-94599)
connected to V
SWITCH
on the way down, the STK12C68-5
CC
and a 68 μF capacitor on V
OH
of at least 2.2V,
Page 5 of 18
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