S29GL128P10TFI020 Spansion Inc., S29GL128P10TFI020 Datasheet - Page 77

• Manufacturer Part Number: S29GL128P10TFI020
• Description: IC 128M PAGE-MODE FLASH MEMORY
• Manufacturer: Spansion Inc.

Specifications of S29GL128P10TFI020

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 24/23Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 16M/8M
• Supply Current: 110mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Compliant

14. Revision History
November 17, 2010 S29GL-P_00_A13
Revision A0 (October 29, 2004)
Revision A1 (October 20, 2005)
Global
Revision A2 (October 19, 2006)
Global
Revision A3 (November 21, 2006)
AC Characteristics
Revision A4 (December 18, 2006)
Global
Write Buffer Programming, Sector
Erase
Password Protection Method
Read-only Operations table
Program and Erase Operations tables
TSOP Pin and BGA Capacitance table
Revision A5 (May 18, 2007)
Global
Performance Characteristics
Hardware Reset
AC Characteristics
Command Definitions tables
DC Characteristics
Page Read Timings figure
Revision A6 (October 23, 2007)
Performance Characteristics
Ordering Information
64-Ball Fortified BGA
56-Pin TSOP
Autoselect
Accelerated Program
Persistent Protection Bits
Secured Silicon Sector
Power-up Sequence Timing
Advance Information on S29GL-R
65 nm MirrorBit Hardware Reset
(RESET#) and Power-up Sequence
Global
Revision A7 (November 8, 2007)
Advance Information on S29GL-R 65
nm MirrorBit Hardware Reset (RESET#)
and Power-up Sequence
Section
Initial Release.
Revised all sections of document.
Revised all sections of document. Reformatted document to new template. Changed speed options
for S29GL01GP.
Erase and Program Operations table: Changed t
Changed t
speed options.
Write Buffer Programming Operation, Sector Erase Operation figures: Deleted “Wait 4 ms” box from
flowcharts.
Lock Register Program Algorithm figure: Deleted “Wait 4 ms” box from flowchart.
Modified t
Changed t
Changed all specifications in table.
Changed data sheet status to Preliminary.
Deleted references to requirement for external WP# pull-up.
Max. Read Access Times table: Added note.
Deleted note from section.
Reset Timings figure: Deleted note.
S29GL-P Sector Protection Command Definitions tables: Changed “Global Non-Volatile Freeze” to
“Global Volatile Freeze”.
CMOS Compatible table: Changed I
Corrected address range for top waveform.
Changed speed options for S29GL512P
Corrected samples OPN valid combinations; changed speed options for S29GL512P
Clarified ball “D1” connection
Clarified pin “30” connection
Added recommendation statement
Added recommendation statement
Removed “Erase” from title and flow chart
Sections “Factory Locked Secured Silicon Sector” & “Customer Lockable Secured Silicon Sector”:
clarified shipping options
Changed t
Added section
Fixed cross-references that were not live hyperlinks.
Changed timing specs and waveforms
D a t a
RC
ACC
DS
RH
S29GL-P MirrorBit
, t
specification, deleted write cycle time note.
from “Max” to “Min” value
, t
ACC
CE
S h e e t
, t
specifications on 128 Mb, 256 Mb, and 512 Mb devices. Added 90 and 100 ns
CE
, t
OE
specifications.
®
Flash Family
CC1
maximum current for 5 MHz and MHz test conditions.
Description
BUSY
to a maximum specification.
77