PIC24HJ16GP304-H/ML Microchip Technology, PIC24HJ16GP304-H/ML Datasheet - Page 19
![16-bit MCU, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24HJ16GP304-H/ML
Manufacturer Part Number
PIC24HJ16GP304-H/ML
Description
16-bit MCU, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP202-ISO.pdf
(272 pages)
3.PIC24HJ32GP202-ISO.pdf
(8 pages)
4.PIC24HJ32GP202-ISO.pdf
(12 pages)
Specifications of PIC24HJ16GP304-H/ML
Core Processor
PIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ16GP304-H/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP202-ISO PDF datasheet #2
- PIC24HJ32GP202-ISO PDF datasheet #3
- PIC24HJ32GP202-ISO PDF datasheet #4
- Current page: 19 of 272
- Download datasheet (4Mb)
3.0
The PIC24HJ32GP202/204 and PIC24HJ16GP304
CPU modules have a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and
addressing modes. The CPU has a 24-bit instruction
word with a variable length opcode field. The Program
Counter (PC) is 23 bits wide and addresses up to
4M x 24 bits of user program memory space. The
actual amount of program memory implemented varies
by
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double word move
(MOV.D)
Overhead-free, single-cycle program loop constructs
are supported using the REPEAT instruction, which is
interruptible at any point.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices have sixteen, 16-bit working registers in the
programmer’s model. Each of the working registers can
serve as a data, address or address offset register. The
16th working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
instruction set includes many addressing modes and is
designed for optimum C compiler efficiency. For most
instructions,
PIC24HJ16GP304 is capable of executing a data (or
program data) memory read, a working register (data)
read, a data memory write and a program (instruction)
memory read per instruction cycle. As a result, three
parameter instructions can be supported, allowing
A + B = C operations to be executed in a single cycle.
A block diagram of the CPU is shown in
programmer’s model for the PIC24HJ32GP202/204
and PIC24HJ16GP304 is shown in
© 2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
device.
2: Some registers and associated bits
CPU
instruction
PIC24HJ32GP202/204 AND PIC24HJ16GP304
of
PIC24HJ16GP304 family of devices.
However, it is not intended to be a com-
prehensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 2. CPU” (DS70204) of
the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available from the
Microchip website (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
A
the
the
single-cycle
and
PIC24HJ32GP202/204
PIC24HJ32GP202/204
the
instruction
table
Figure
Figure
instructions.
3-2.
prefetch
3-1. The
and
and
in
3.1
The data space can be linearly addressed as 32K words
or 64 Kbytes using an Address Generation Unit (AGU).
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K pro-
gram word boundary defined by the 8-bit Program Space
Visibility Page register (PSVPAG). The program to data
space mapping feature lets any instruction access pro-
gram space as if it were data space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but this
may be used as general purpose RAM.
3.2
The PIC24HJ32GP202/204 and PIC24HJ16GP304
feature a 17-bit by 17-bit, single-cycle multiplier. The
multiplier
mixed-sign multiplication. Using a 17-bit by 17-bit
multiplier for 16-bit by 16-bit multiplication makes
mixed-sign multiplication possible.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
supports 16/16 and 32/16 integer divide operations. All
divide instructions are iterative operations. They must
be executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.
Data Addressing Overview
Special MCU Features
can
perform
signed,
DS70289G-page 19
unsigned
and
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