PIC24HJ16GP304-H/ML Microchip Technology, PIC24HJ16GP304-H/ML Datasheet - Page 183
![16-bit MCU, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24HJ16GP304-H/ML
Manufacturer Part Number
PIC24HJ16GP304-H/ML
Description
16-bit MCU, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP202-ISO.pdf
(272 pages)
3.PIC24HJ32GP202-ISO.pdf
(8 pages)
4.PIC24HJ32GP202-ISO.pdf
(12 pages)
Specifications of PIC24HJ16GP304-H/ML
Core Processor
PIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ16GP304-H/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP202-ISO PDF datasheet #2
- PIC24HJ32GP202-ISO PDF datasheet #3
- PIC24HJ32GP202-ISO PDF datasheet #4
- Current page: 183 of 272
- Download datasheet (4Mb)
TABLE 20-2:
© 2011 Microchip Technology Inc.
35
36
37
38
39
40
41
42
43
44
45
46
Base
Instr
#
INC
INC2
IOR
LNK
LSR
MOV
MUL
NEG
NOP
POP
PUSH
PWRSAV
Mnemonic
Assembly
PIC24HJ32GP202/204 AND PIC24HJ16GP304
INSTRUCTION SET OVERVIEW (CONTINUED)
INC
INC
INC
INC2
INC2
INC2
IOR
IOR
IOR
IOR
IOR
LNK
LSR
LSR
LSR
LSR
LSR
MOV
MOV
MOV
MOV
MOV.b
MOV
MOV
MOV
MOV.D
MOV.D
MUL.SS
MUL.SU
MUL.US
MUL.UU
MUL.SU
MUL.UU
MUL
NEG
NEG
NEG
NOP
NOPR
POP
POP
POP.D
POP.S
PUSH
PUSH
PUSH.D
PUSH.S
PWRSAV
f
f,WREG
Ws,Wd
f
f,WREG
Ws,Wd
f
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
#lit14
f
f,WREG
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,Wn
f
f,WREG
#lit16,Wn
#lit8,Wn
Wn,f
Wso,Wdo
WREG,f
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,#lit5,Wnd
Wb,#lit5,Wnd
f
f
f,WREG
Ws,Wd
f
Wdo
Wnd
f
Wso
Wns
Assembly Syntax
#lit1
Wns,Wd
Ws,Wnd
f = f + 1
WREG = f + 1
Wd = Ws + 1
f = f + 2
WREG = f + 2
Wd = Ws + 2
f = f .IOR. WREG
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
Wd = Wb .IOR. Ws
Wd = Wb .IOR. lit5
Link Frame Pointer
f = Logical Right Shift f
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Move f to Wn
Move f to f
Move f to WREG
Move 16-bit literal to Wn
Move 8-bit literal to Wn
Move Wn to f
Move Ws to Wd
Move WREG to f
Move Double from W(ns):W(ns + 1) to Wd
Move Double from Ws to W(nd + 1):W(nd)
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
W3:W2 = f * WREG
f = f + 1
WREG = f + 1
Wd = Ws + 1
No Operation
No Operation
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
Pop Shadow Registers
Push f to Top-of-Stack (TOS)
Push Wso to Top-of-Stack (TOS)
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
Push Shadow Registers
Go into Sleep or Idle mode
Description
Words
# of
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycles
DS70289G-page 183
# of
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
Status Flags
WDTO,Sleep
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
Affected
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
N,Z
N,Z
N,Z
N,Z
N,Z
N,Z
N,Z
N,Z
All
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