PIC24FJ32GA102-E/SS Microchip Technology, PIC24FJ32GA102-E/SS Datasheet - Page 178

• Manufacturer Part Number: PIC24FJ32GA102-E/SS
• Description: 16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GA102-E/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 300 mA
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Eeprom Size: -
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC24FJ64GA104 FAMILY
REGISTER 16-1:
DS39951C-page 178
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
I2CEN
GCEN
R/W-0
R/W-0
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module, and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module. All I
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
0 = Continues module operation in Idle mode
SCLREL: SCLx Release Control bit (when operating as I
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit
1 = IPMI Support mode is enabled; all addresses Acknowledged
0 = IPMI mode is disabled
A10M: 10-Bit Slave Addressing bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with the SMBus specification
0 = Disables the SMBus input thresholds
GCEN: General Call Enable bit (when operating as I
1 = Enables interrupt when a general call address is received in the I2CxRSR
0 = General call address is disabled
STREN: SCLx Clock Stretch Enable bit (when operating as I
Used in conjunction with the SCLREL bit.
1 = Enables software or receive clock stretching
0 = Disables software or receive clock stretching
STREN
R/W-0
(module is enabled for reception)
U-0
—
I2CxCON: I2Cx CONTROL REGISTER
HC = Hardware Clearable bit
W = Writable bit
‘1’ = Bit is set
I2CSIDL
ACKDT
R/W-0
R/W-0
R/W-1, HC
R/W-0, HC
SCLREL
ACKEN
2
C pins are controlled by port functions.
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0, HC
IPMIEN
R/W-0
RCEN
2
C slave)
2
C Slave)
R/W-0, HC
2
C slave)
R/W-0
A10M
PEN
 2010 Microchip Technology Inc.
x = Bit is unknown
R/W-0, HC
DISSLW
R/W-0
RSEN
R/W-0, HC
SMEN
R/W-0
SEN
bit 8
bit 0