PIC24FJ256GA106-E/PT Microchip Technology, PIC24FJ256GA106-E/PT Datasheet - Page 9

• Manufacturer Part Number: PIC24FJ256GA106-E/PT
• Description: 16-bit, 16 MIPS, 256KB Flash, 16Kb RAM, 53 I/O, NanoWatt 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GA106-E/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9. Module: 10-Bit High-Speed A/D
REGISTER 20-1:
© 2009 Microchip Technology Inc.
bit 7-5
In Register 20-1 (AD1CON1), the descriptions
provided for the various combinations of the
SSRC<2:0> bits (ADCON1<7:5>) are incorrect.
Specifically, while the number and type of trigger
sources are reported correctly, several are
associated with the wrong bit combinations.
The correct order of trigger sources is listed below
(changes in bold).
Converter
SSRC2:SSRC0: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = CTMU event ends sampling and starts conversion
101 = Reserved
100 = Timer5 compare ends sampling and starts conversion
011 = Reserved
010 = Timer3 compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing SAMP bit ends sampling and starts conversion
AD1CON1: A/D CONTROL REGISTER 1 (PARTIAL REPRESENTATION)
PIC24FJ256GA110 FAMILY
10. Module: Special Features
In Register 24-3 (CW3), the explanatory text with
Configuration bits, WPFP<8:0> (CW3<8:0>), is
changed to agree with the text of Section 24.4.2
“Code Segment Protection”. The new register
text is as follows (change in bold):
“Designates the 512-byte program code page that
is the boundary of the protected code segment,
starting with Page 0 at the bottom of program
memory.”
DS80385B-page 9