PIC24FJ256GA106-E/PT Microchip Technology, PIC24FJ256GA106-E/PT Datasheet - Page 6
![16-bit, 16 MIPS, 256KB Flash, 16Kb RAM, 53 I/O, NanoWatt 64 TQFP 10x10x1mm TRAY](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC24FJ256GA106-E/PT
Manufacturer Part Number
PIC24FJ256GA106-E/PT
Description
16-bit, 16 MIPS, 256KB Flash, 16Kb RAM, 53 I/O, NanoWatt 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA008-IPT.pdf
(12 pages)
2.PIC24FJ128GA106-IPT.pdf
(14 pages)
3.PIC24FJ128GA106-IPT.pdf
(330 pages)
4.PIC24FJ128GA106-IPT.pdf
(52 pages)
5.PIC24FJ256GA106-IPT.pdf
(59 pages)
Specifications of PIC24FJ256GA106-E/PT
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (85.5K x 24)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ256GA106-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC24FJ256GA110 FAMILY
4. Module: Pin Diagrams
5. Module: Memory Organization
DS80385B-page 6
In the 64-pin device pin diagram on page 2, the
reference to SCK1 on pin 35 is deleted. The
correct complete designation for this pin is “RPI45/
INT0/CN72/RF6”.
The SCK1 function is available only through Periph-
eral Pin Select (PPS), and is not permanently
multiplexed to any one pin on this device.
In Table 3-5 of the device data sheet (Interrupt
Controller Register Map), bits 4 and 3 of INTCON2
are incorrectly shown as unimplemented. These
positions are actually implemented as INT4EP and
INT3EP, respectively.
An amended partial version of the table with the
correct footnote is shown in Table 3-5 (additions in
bold).
(SFR Space)
6. Module: Memory Organization
In Table 3-18 of the device data sheet (PORTG
Register Map), the footnote references on the Bit 1
and Bit 0 columns are incorrect. These bits, and
their corresponding I/O channels, are actually
available on 80-pin devices.
An amended version of the table with the correct
footnote is shown in Table 3-18 (additions and
changes in bold).
(SFR Space)
© 2009 Microchip Technology Inc.