PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet - Page 42

• Manufacturer Part Number: PIC24F04KA200T-I/ST
• Description: PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F04KA200T-I/ST

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (1.375K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24FXXKAXXX
TABLE 5-5:
5.5
After the programming executive is programmed to the
executive memory using ICSP, it must be verified.
Verify by reading out the contents of the executive
memory and comparing it with the image of the
programming executive stored in the programmer.
Read the contents of the executive memory using the
same method described in Section 3.9 “Reading
Code Memory”.
DS39919A-page 42
Step 18: Load the saved Diagnostic Words in last eight write latches.
Step 19: Repeat Steps 13 through 15.
Command
(Binary)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Programming Verification
PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED)
BB1A86
000000
000000
BB1A87
000000
000000
BB1A88
000000
000000
BB1A89
000000
000000
BB1A8A
000000
000000
BB1A8B
000000
000000
BB1A8C
000000
000000
BB1A8D
000000
000000
(Hex)
Data
TBLWTL
NOP
NOP
TBLWTL
NOP
NOP
TBLWTL
NOP
NOP
TBLWTL
NOP
NOP
TBLWTL
NOP
NOP
TBLWTL
NOP
NOP
TBLWTL
NOP
NOP
TBLWTL
NOP
NOP
Advance Information
W6, [W5++]
W7, [W5++]
W8, [W5++]
W9, [W5++]
W10, [W5++]
W11, [W5++]
W12, [W5++]
W13, [W5++]
Table provides the procedure for reading the executive
memory.
Note:
Description
In Step 2 of Table 5-6, the TBLPAG
register is set to 80h, such that the
executive memory may be read.
© 2008 Microchip Technology Inc.