PIC18LF23K22-E/SO Microchip Technology, PIC18LF23K22-E/SO Datasheet - Page 213
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PIC18LF23K22-E/SO
Manufacturer Part Number
PIC18LF23K22-E/SO
Description
8KB, Flash, 768bytes-RAM,8-bit Family,nanoWatt XLP 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F26J13-ISS.pdf
(496 pages)
Specifications of PIC18LF23K22-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (0.300", 7.50mm Width)
Processor Series
PIC18LF
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.2.3
The master can initiate the data transfer at any time
because it controls the SCKx line. The master
determines when the slave (Processor 2,
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDOx output could be dis-
abled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx
pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
FIGURE 15-6:
2010 Microchip Technology Inc.
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
SDOx
(CKE = 0)
SDOx
(CKE = 1)
SDIx
(SMP = 0)
Input
Sample
(SMP = 0)
SDIx
(SMP = 1)
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF
SPI MASTER MODE
SPI MODE WAVEFORM (MASTER MODE)
bit 7
bit 7
bit 7
bit 7
bit 6
bit 6
Figure
bit 5
bit 5
15-5)
Preliminary
bit 4
bit 4
bit 3
bit 3
The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
and the CKE bit of the SSPxSTAT register. This then,
would give waveforms for SPI communication as
shown in
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
• F
• F
• F
• Timer2 output/2
• F
Figure 15-6
When the CKE bit is set, the SDOx data is valid before
there is a clock edge on SCKx. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
PIC18(L)F2X/4XK22
OSC
OSC
OSC
OSC
/4 (or T
/16 (or 4 * T
/64 (or 16 * T
/(4 * (SSPxADD + 1))
bit 2
bit 2
Figure
shows the waveforms for Master mode.
CY
)
bit 1
bit 1
15-6,
CY
CY
)
)
Figure 15-8
bit 0
bit 0
bit 0
bit 0
DS41412D-page 213
and
4 Clock
Modes
Figure
15-9,
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