PIC18LF23K22-E/SO Microchip Technology, PIC18LF23K22-E/SO Datasheet - Page 171
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PIC18LF23K22-E/SO
Manufacturer Part Number
PIC18LF23K22-E/SO
Description
8KB, Flash, 768bytes-RAM,8-bit Family,nanoWatt XLP 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F26J13-ISS.pdf
(496 pages)
Specifications of PIC18LF23K22-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (0.300", 7.50mm Width)
Processor Series
PIC18LF
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12.14 Timer1/3/5 Gate Control Register
The Timer1/3/5 Gate Control register (TxGCON),
shown in
Gate.
REGISTER 12-2:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
TMRxGE
R/W-0/u
Register
TMRxGE: Timer1/3/5 Gate Enable bit
If TMRxON = 0:
This bit is ignored
If TMRxON = 1:
1 = Timer1/3/5 counting is controlled by the Timer1/3/5 gate function
0 = Timer1/3/5 counts regardless of Timer1/3/5 gate function
TxGPOL: Timer1/3/5 Gate Polarity bit
1 = Timer1/3/5 gate is active-high (Timer1/3/5 counts when gate is high)
0 = Timer1/3/5 gate is active-low (Timer1/3/5 counts when gate is low)
TxGTM: Timer1/3/5 Gate Toggle Mode bit
1 = Timer1/3/5 Gate Toggle mode is enabled
0 = Timer1/3/5 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1/3/5 gate flip-flop toggles on every rising edge.
TxGSPM: Timer1/3/5 Gate Single-Pulse Mode bit
1 = Timer1/3/5 gate Single-Pulse mode is enabled and is controlling Timer1/3/5 gate
0 = Timer1/3/5 gate Single-Pulse mode is disabled
TxGGO/DONE: Timer1/3/5 Gate Single-Pulse Acquisition Status bit
1 = Timer1/3/5 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1/3/5 gate single-pulse acquisition has completed or has not been started
This bit is automatically cleared when TxGSPM is cleared.
TxGVAL: Timer1/3/5 Gate Current State bit
Indicates the current state of the Timer1/3/5 gate that could be provided to TMRxH:TMRxL.
Unaffected by Timer1/3/5 Gate Enable (TMRxGE).
TxGSS<1:0>: Timer1/3/5 Gate Source Select bits
00 = Timer1/3/5 Gate pin
01 = Timer2/4/6 Match PR2/4/6 output (See
10 = Comparator 1 optionally synchronized output (SYNCC1OUT)
11 = Comparator 2 optionally synchronized output (SYNCC2OUT)
TxGPOL
R/W-0/u
12-2, is used to control Timer1/3/5
TXGCON: TIMER1/3/5 GATE CONTROL REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/u
TxGTM
TxGSPM
R/W-0/u
Preliminary
HC = Bit is cleared by hardware
TxGGO/DONE
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
Table 12-6
R/W/HC-0/u
PIC18(L)F2X/4XK22
for proper timer match selection)
TxGVAL
R-x/x
R/W-0/u
TxGSS<1:0>
DS41412D-page 171
R/W-0/u
bit 0
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