PIC18LF23K22-E/SO Microchip Technology, PIC18LF23K22-E/SO Datasheet - Page 123
![8KB, Flash, 768bytes-RAM,8-bit Family,nanoWatt XLP 28 SOIC .300in TUBE](/photos/28/69/286927/28-soic_m28b_sml.jpg)
PIC18LF23K22-E/SO
Manufacturer Part Number
PIC18LF23K22-E/SO
Description
8KB, Flash, 768bytes-RAM,8-bit Family,nanoWatt XLP 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F26J13-ISS.pdf
(496 pages)
Specifications of PIC18LF23K22-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (0.300", 7.50mm Width)
Processor Series
PIC18LF
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.6
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are five Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3, PIE4 and
PIE5). When IPEN = 0, the PEIE/GIEL bit must be set to
enable any of these peripheral interrupts.
REGISTER 9-9:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
PIE Registers
Unimplemented: Read as ‘0’.
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
RC1IE: EUSART1 Receive Interrupt Enable bit
1 = Enables the EUSART1 receive interrupt
0 = Disables the EUSART1 receive interrupt
TX1IE: EUSART1 Transmit Interrupt Enable bit
1 = Enables the EUSART1 transmit interrupt
0 = Disables the EUSART1 transmit interrupt
SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit
1 = Enables the MSSP1 interrupt
0 = Disables the MSSP1 interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R/W-0
ADIE
PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1
W = Writable bit
‘1’ = Bit is set
RC1IE
R/W-0
R/W-0
TX1IE
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSP1IE
R/W-0
PIC18(L)F2X/4XK22
CCP1IE
R/W-0
x = Bit is unknown
TMR2IE
R/W-0
DS41412D-page 123
TMR1IE
R/W-0
bit 0
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