PIC18LF14K22-E/P Microchip Technology, PIC18LF14K22-E/P Datasheet - Page 23
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PIC18LF14K22-E/P
Manufacturer Part Number
PIC18LF14K22-E/P
Description
16KB Flash, 512bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 PDIP .300in T
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18LF13K22-ISS.pdf
(388 pages)
Specifications of PIC18LF14K22-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2.8
The Primary External Oscillator, when configured for
LP, XT or HS modes, incorporates an Oscillator Start-
up Timer (OST). The OST ensures that the oscillator
starts and provides a stable clock to the oscillator
module. The OST times out when 1024 oscillations on
OSC1 have occurred. During the OST period, with the
system clock set to the Primary External Oscillator, the
program counter does not increment suspending
program execution. The OST period will occur
following:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Wake-up from Sleep
• Oscillator being enabled
• Expiration of Power-up Timer (PWRT)
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Start-up
mode can be selected. See Section 2.11 “Two-Speed
Start-up Mode” for more information.
FIGURE 2-5:
2010 Microchip Technology Inc.
New Clk Ready
New Clk Ready
Low Speed
High Speed
System Clock
System Clock
IRCF <2:0>
Note 1: Start-up time includes T
IRCF <2:0>
New Clock
New Clock
Old Clock
Oscillator Start-up Timer
Old Clock
Select Old
High Speed
Low Speed
Select Old
CLOCK SWITCH TIMING
Start-up Time
Start-up Time
OST
(1024 T
(1)
Select New
Select New
(1)
OSC
) for external clocks, plus T
Preliminary
PIC18F1XK22/LF1XK22
Clock Sync
2.9
The device contains circuitry to prevent clock “glitches”
due to a change of the system clock source. To
accomplish this, a short pause in the system clock
occurs during the clock switch. If the new clock source
is not stable (e.g., OST is active), the device will
continue to execute from the old clock source until the
new clock source becomes stable. The timing of a
clock switch is as follows:
1.
2.
3.
4.
5.
6.
7.
Refer to Figure 2-5 for more details.
Clock Sync
SCS<1:0> bits of the OSCCON register are
modified.
The system clock will continue to operate from
the old clock until the new clock is ready.
Clock switch circuitry waits for two consecutive
rising edges of the old clock after the new clock
is ready.
The system clock is held low, starting at the next
falling edge of the old clock.
Clock switch circuitry waits for an additional two
rising edges of the new clock.
On the next falling edge of the new clock, the
low hold on the system clock is release and the
new clock is switched in as the system clock.
Clock switch is complete.
Clock Switching
PLL
(approx. 2 ms) for HSPLL mode.
Running
Running
DS41365D-page 23
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