PIC18LF14K22-E/P Microchip Technology, PIC18LF14K22-E/P Datasheet - Page 117
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18LF14K22-E/P
Manufacturer Part Number
PIC18LF14K22-E/P
Description
16KB Flash, 512bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 PDIP .300in T
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18LF13K22-ISS.pdf
(388 pages)
Specifications of PIC18LF14K22-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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13.4
The Enhanced PWM mode can generate a PWM signal
on up to four different output pins with up to 10-bits of
resolution. It can do this through four different PWM
output modes:
• Single PWM
• Half-Bridge PWM
• Full-Bridge PWM, Forward mode
• Full-Bridge PWM, Reverse mode
To select an Enhanced PWM mode, the P1M bits of the
CCP1CON register must be set appropriately.
FIGURE 13-3:
TABLE 13-2:
2010 Microchip Technology Inc.
ECCP Mode
Single
Half-Bridge
Full-Bridge, Forward
Full-Bridge, Reverse
Note 1:
Note 1: The TRIS register value for each PWM output must be configured appropriately.
CCPR1H (Slave)
Duty Cycle Registers
Note 1:
Comparator
2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
PWM (Enhanced Mode)
CCPR1L
PR2
TMR2
Comparator
Outputs are enabled by pulse steering in Single mode. See Register 13-4.
The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit
time base.
EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
(1)
EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
Clear Timer2,
toggle PWM pin and
latch duty cycle
DC1B<1:0>
P1M<1:0>
00
10
01
11
R
S
P1M<1:0>
Q
CCP1/P1A
Yes
Preliminary
Yes
Yes
Yes
(1)
PWM1CON
Controller
PIC18F1XK22/LF1XK22
Output
2
CCP1/P1A
P1B
P1C
P1D
The PWM outputs are multiplexed with I/O pins and are
designated P1A, P1B, P1C and P1D. The polarity of the
PWM pins is configurable and is selected by setting the
CCP1M bits in the CCP1CON register appropriately.
Table 13-1 shows the pin assignments for each
Enhanced PWM mode.
Figure 13-3 shows an example of a simplified block
diagram of the Enhanced PWM module.
4
CCP1M<3:0>
Note:
Yes
P1B
Yes
Yes
Yes
TRIS
TRIS
TRIS
TRIS
(1)
To
incomplete waveform when the PWM is
first enabled, the ECCP module waits until
the start of a new PWM period before
generating a PWM signal.
prevent
Yes
P1C
Yes
Yes
No
the
(1)
CCP1/P1A
P1B
P1D
P1C
generation
DS41365D-page 117
Yes
P1D
Yes
Yes
No
(1)
of
an
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