PIC18LF14K22-E/P Microchip Technology, PIC18LF14K22-E/P Datasheet - Page 22
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PIC18LF14K22-E/P
Manufacturer Part Number
PIC18LF14K22-E/P
Description
16KB Flash, 512bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 PDIP .300in T
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18LF13K22-ISS.pdf
(388 pages)
Specifications of PIC18LF14K22-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F1XK22/LF1XK22
2.7.1
The HFINTOSC is factory calibrated, but can be
adjusted in software by writing to the TUN<5:0> bits of
the OSCTUNE register (Register 2-3).
The default value of the TUN<5:0> is ‘000000’. The
value is a 6-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift,
while giving no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
The operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
REGISTER 2-3:
DS41365D-page 22
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-0
INTSRC
R/W-0
OSCTUNE REGISTER
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 16 MHz HFINTOSC source (divide-by-512 enabled)
0 = 31 kHz device clock derived directly from LFINTOSC internal oscillator
PLLEN: Frequency Multiplier PLL bit
1 = PLL enabled (for HFINTOSC 8 MHz and 16 MHz only)
0 = PLL disabled
TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
011110 =
000001 =
000000 = Oscillator module is running at the factory calibrated frequency.
111111 =
100000 = Minimum frequency
• • •
• • •
PLLEN
R/W-0
OSCTUNE: OSCILLATOR TUNING REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
TUN5
R/W-0
TUN4
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock Mon-
itor (FSCM) and peripherals, are not affected by the
change in frequency.
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in greater
detail in Section 2.6.1 “LFINTOSC”.
The PLLEN bit controls the operation of the frequency
multiplier. For more details about the function of the
PLLEN bit see Section 2.10 “4x Phase Lock Loop
Frequency Multiplier”
TUN3
R/W-0
TUN2
2010 Microchip Technology Inc.
x = Bit is unknown
R/W-0
TUN1
R/W-0
TUN0
bit 0
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