PIC18LF13K22-E/P Microchip Technology, PIC18LF13K22-E/P Datasheet - Page 6

• Manufacturer Part Number: PIC18LF13K22-E/P
• Description: 8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 PDIP .300in TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
DS80437D-page 6
3.2
Affected Silicon Revisions
3.3
Affected Silicon Revisions
3.4
Affected Silicon Revisions
A3
A3
A3
X
X
X
Work around
Work around
bit in lieu of clearing the SPEN bit.
Work around
instructions, immediately following setting
the SPEN bit to ‘1’.
reset only by either clearing the CREN bit of
the RCSTA register or by a device Reset.
Clearing the SPEN bit of the RCSTA register
does not clear the OERR flag.
Clear the OERR flag by clearing the CREN
set and the CREN bit of the RCSTA register
is clear, the RX pin is not available for gen-
eral purpose output. Likewise, when the
SPEN bit of the RCSTA register is set and
the TXEN bit of the TXSTA register is clear,
the TX pin is not available for general pur-
pose output. However, both the RX and TX
pins can be read regardless of the state of
the RCSTA and TXSTA control registers.
None.
disabled and then re-enabled with the
EUSART receive interrupt and global inter-
rupts enabled, then a single cycle instruction
is followed by a 2 cycle instruction.
Always execute at least 2 single-cycle
The OERR flag of the RCSTA register is
When the SPEN bit of the RCSTA register is
Unexpected results occur if the EUSART is
A7
A7
A7
X
X
X
A8
A8
A8
X
X
4. Module: MSSP (Master Synchronous
4.1
Affected Silicon Revisions
4.2
Affected Silicon Revisions
4.3
Affected Silicon Revisions
4.4
Affected Silicon Revisions
A3
A3
A3
A3
X
X
X
X
by setting SSPADD to a value less than
0x03 will cause unexpected operation.
Work around
Ensure SSPADD is set to a value greater
than or equal to 0x03.
cleared and the SMP bit is set, the last bit of
the incoming data stream (bit 0) at the SDI
pin will not be sampled properly.
Work around
None.
CKE = 1 and CKP = 0, a 1/F
will occur on the SCK pin.
Work around
Configure the SCK pin as an input until after
the MSSP is setup.
0x00, 0x01, 0x02 are invalid. The current I
Baud Rate Generator (BRG) is not set up to
generate a clock signal for these values.
Work around
None.
In I
In SPI Master mode, when the CKE bit is
When SPI is enabled in Master mode with
In I
A7
A7
A7
A7
X
X
X
X
2
2
C™ Master mode, baud rates obtained
C Master mode, SSPADD values of
Serial Port)
A8
A8
A8
A8
X
X
X
X
 2010 Microchip Technology Inc.
OSC
wide pulse
2
C