PIC18LF13K22-E/P Microchip Technology, PIC18LF13K22-E/P Datasheet - Page 3

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PIC18LF13K22-E/P

Manufacturer Part Number
PIC18LF13K22-E/P
Description
8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 PDIP .300in TU
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-E/P

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Silicon Errata Issues
1. Module: ADC (Analog-to-Digital
 2010 Microchip Technology Inc.
Note:
1.1
Affected Silicon Revisions
A3
X
large INL error up to approximately 8 LSb.
Work around
None for the AN3 pin. For better accuracy,
use another analog pin.
ADC conversion on AN3/OSC2 will have
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A8).
A7
X
Converter)
A8
X
PIC18F1XK22/LF1XK22
1.2
1. When F
2. The ADC is operating from its dedicated
Work around
Method 1:
Method 2: Select the dedicated FRC
Method 3: Method 3 is provided if the
these conditions:
An ADC conversion may not complete under
the clock source used for the ADC
converter.
internal FRC oscillator and the device is
not in Sleep mode (an F
When this occurs, the ADC Interrupt
Fag (ADIF) does not get set, the GO/
DONE bit does not get cleared, and the
conversion result does not get loaded
into the ADRESH and ADRESL result
registers.
OSC
as the ADC clock source and
reduce the F
MHz or less when performing
ADC conversions.
oscillator
conversion clock source and
perform all conversions with the
device in Sleep.
application cannot use Sleep
mode and requires continuous
operation at frequencies above
8 MHz. This method requires
early termination of an ADC
conversion. Provide a fixed time
delay in software to stop the A-
to-D conversion manually, after
all 10 bits are converted, but
before the conversion would
complete
conversion
clearing the GO/DONE bit in
software. The GO/DONE bit
must be cleared during the last
½
conversion
completed automatically. Refer
to Figure 1 for details.
Select the system clock, F
is greater than 8 MHz and is
T
AD
cycle,
automatically.
OSC
as
OSC
is
DS80437D-page 3
would
frequency to 8
frequency).
stopped
before
the
have
ADC
OSC
The
the
by
,

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