PIC18LF13K22-E/P Microchip Technology, PIC18LF13K22-E/P Datasheet - Page 5

• Manufacturer Part Number: PIC18LF13K22-E/P
• Description: 8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 PDIP .300in TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In Figure 1, 88 instruction cycles (T
to complete the full conversion. Each T
consists of 8 T
stop the A/D conversion after 86 instruction cycles and
terminate the conversion at the correct time as shown
in the figure above.
EXAMPLE 1:
For other combinations of F
Instruction cycle delay counts, refer to Table 3.
TABLE 3:
 2010 Microchip Technology Inc.
BSF
BCF
MOVF
Note:
Affected Silicon Revisions
F
F
F
A3
OSC
OSC
OSC
X
T
AD
ADCON0, GO
ADCON0, GO
ADRESH, W
/64
/32
/16
The exact delay time will depend on the
T
counts shown in the timing diagram above
apply to this example only. Refer to
Table 3 for the required delay counts for
other configurations.
A7
AD
X
CY
INSTRUCTION CYCLE DELAY
COUNT VS. T
divisor (ADCS) selection. The T
periods. A fixed delay is provided to
A8
Instruction Cycle Delay Counts
CODE EXAMPLE OF
INSTRUCTION CYCLE
DELAY
; Start ADC conversion
; Provide 86
; Terminate the
; Read conversion
instruction cycle
delay here
conversion manually
result
OSC
AD
172
86
43
CY
, T
) will be required
AD
values and
AD
cycle
CY
PIC18F1XK22/LF1XK22
2. Module: ECCP
3. Module: EUSART
2.1
Affected Silicon Revisions
2.2
Affected Silicon Revisions
3.1
Affected Silicon Revisions
A3
A3
A3
X
X
X
Changing direction in Full-Bridge mode
In Full-Bridge mode, when PR2 = CCPR1L,
inserts a dead band time of 4/F
Prescale instead of 1/F
cale as specified in the data sheet.
Work around
DC1B<1:0> = 00, and the direction is
changed, then the dead time before the
modulated output starts is compromised.
The modulated signal improperly starts
immediately with the direction change and
stays
DC1B<1:0>.
Work around
cycle is within three least significant steps of
100%
DC1B<1:0> bits before the direction change
and then set them to the desired value after
the direction change is complete.
bit of the BAUDCON register will properly go
low when a low pulse greater than 1/16
a bit time is received on the RX input. The
RCIDL bit will then improperly go high if a low
pulse less than 1/16 bit time occurs on the
RX input within one bit period, after the fall-
ing edge of the first pulse. This erratum
affects only users monitoring the RCIDL bit
as a part of their serial protocol.
Work around
None.
Avoid changing direction when the duty
None.
In Asynchronous Receive mode, the RCIDL
A7
A7
A7
X
X
X
on
duty
A8
A8
A8
X
X
X
for
cycle.
T
OSC
Instead,
* TMR2
OSC
DS80437D-page 5
* TMR2 Pres-
OSC
clear
Prescale *
* TMR2
th
the
of