PIC18F87K90-E/PT Microchip Technology, PIC18F87K90-E/PT Datasheet - Page 440

• Manufacturer Part Number: PIC18F87K90-E/PT
• Description: 128kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TR
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F87K90-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K90 FAMILY
28.2
For the PIC18F87K90 family of devices, the WDT is
driven by the LF-INTOSC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
LF-INTOSC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 4,194 seconds (about one hour). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEP or CLRWDT instruction
is executed, the IRCF bits (OSCCON<6:4>) are
changed or a clock failure has occurred.
FIGURE 28-1:
DS39957D-page 440
WDT Disabled in Hardware,
Change on IRCF<2:0> bits
WDTEN0
WDTEN1
WDT Enabled only While
Device Active, Disabled
WDT Controlled with
SWDTEN bit Setting
Watchdog Timer (WDT)
SWDTEN Disabled
SWDTEN Disabled
All Device Resets
WDT Enabled,
INTRC Source
WDTPS<3:0>
CLRWDT
Sleep
WDT BLOCK DIAGRAM
Enable WDT
WDT Counter
 128
4
Programmable Postscaler
1:1 to 1:1,048,576
The WDT can be operated in one of four modes as
determined by the CONFIG2H bits (WDTEN<1:0>) The
four modes are:
• WDT Enabled
• WDT Disabled
• WDT under Software Control (WDTCON<0>,
• WDT
INTRC Source
SWDTEN)
- Enabled during normal operation
- Disabled during Sleep
Note 1: The CLRWDT and SLEEP instructions
WDTEN<1:0>
SWDTEN
2: Changing the setting of the IRCF bits
3: When a CLRWDT instruction is executed,
clear the WDT and postscaler counts
when executed.
(OSCCON<6:4>) clears the WDT and
postscaler counts.
the postscaler count will be cleared.
 2009-2011 Microchip Technology Inc.
Reset
Enable WDT
Wake-up from
Power-Managed
Modes
WDT
Reset